1 / 10

VDHL

VDHL. for Storage Elements. Implied Memory. PROCESS ( A, B ) BEGIN IF A = B THEN AeqB <= '1' ; END IF ; END PROCESS ;. What is the value of AeqB when A <> B? “Semantics specify” that AeqB retains its current value What value does AeqB initialize to?. D Latch.

nevin
Download Presentation

VDHL

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. VDHL for Storage Elements

  2. Implied Memory PROCESS ( A, B ) BEGIN IF A = B THEN AeqB <= '1' ; END IF ; END PROCESS ; What is the value of AeqB when A <> B? “Semantics specify” that AeqB retains its current value What value does AeqB initialize to?

  3. D Latch PROCESS ( D, Clk ) BEGIN IF Clk = '1' THEN Q <= D ; END IF ; END PROCESS ; “Sensitivity list includes both Clk and D because these signals can cause a change in the value of Q”

  4. Positive Edge Triggered D Flip-Flop “sensitivity list contains only the clock signal because it is the only signals that can cause a change in the Q output” PROCESS ( Clock ) BEGIN IF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; EVENT is an attribute a property of the object Clock EVENT attribute refers to any change in the object

  5. Positive Edge Triggered D Flip-Flopusing wait until PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; Q <= D ; END PROCESS ; WAIT UNTIL construct implies sensitivity list only includes clock signal “In our use of VHDL, which is for synthesis of circuits” WAIT UNTIL can appear only as the first statement in a process Could be written WAIT UNTIL Clock=‘1’; but some CAD tools require the ’EVENT attribute

  6. IF vs WAIT UNTIL • When condition Clock’EVENT AND Clock=‘1’ appears in an • IF statement • any signals that are assigned values inside the IF statement are implemented as the outputs of flip-flops • WAIT UNTIL statement • any signal that is assigned a value in the entire process is implemented as the output of a flip-flop

  7. Asynchronous Clear PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= '0' ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ;

  8. Synchronous Clear PROCESS ( Resetn, Clock ) BEGIN WAIT UNTIL Clock’EVENT AND Clock=‘1’ IF Resetn = '0' THEN Q <= '0' ; ELSE Q <= D ; END IF ; END PROCESS ;

  9. Lab • Use VHDL to Create the 4 bit ripple counter in Brown Figure 7.20 • Simulate your 4 bit ripple counter in Quartus • Both Functional and Timing • What is the difference? • What is the fastest clock rate (fmax) for your counter? • Compare your code to the VHDL code in Brown 7.52

  10. Home Work • Brown Section 7.13.1 Schematic Entry of Adder with Register Feedback • Use Timing Simulation to determine fastest speed allowed

More Related