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DSP Innovations in 28-nm FPGAs

DSP Innovations in 28-nm FPGAs. Danny Biran Senior VP of Marketing. Ever-Increasing Bandwidth…. ….Demands ever-increasing processing performance. Stratix V FPGAs – “More Than Moore”. High bandwidth I/O High-speed transceivers up to 28-Gbps (total 1.6 Tbps)

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DSP Innovations in 28-nm FPGAs

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  1. DSP Innovations in 28-nm FPGAs Danny Biran Senior VP of Marketing

  2. Ever-Increasing Bandwidth… ….Demands ever-increasing processing performance

  3. Stratix V FPGAs – “More Than Moore” • High bandwidth I/O • High-speed transceivers up to 28-Gbps (total 1.6 Tbps) • Up to 7 x 72-bit 1,600 Mbps DDR3 interfaces • High performance core • More than 1M logic elements • More than 50 Mb of RAM • High-performance, variable-precision DSP with up to 3,680 18 x 18 multipliers (1,840 GMACS) • Application-targeted hard IP • Power and cost • 3rd Generation Programmable Power Technology • HardCopy V ASIC provides risk-free path to ASIC • New capabilities • Embedded HardCopy Blocks • Partial reconfiguration

  4. Increasing Processing with Strict Power and Cost Budgets Processing Price/Power Time 4

  5. Video Processing Standard Definition 0.4M pixels per frame 9 x 9 precision High Definition (1080p) 2M pixels per frame 9 x 9 → 12 x 12 precision 4K Resolution ~10M pixels per frame 9 x 9 → 18 x 18 precision DSP performance  25X pixels processed per frame

  6. Wireless Evolution 3G LTE Advanced LTE Single antenna 5 MHz, 1 carrier 18 x 18 precision 2 x 2 MIMO 20 MHz, 1 carrier 18 x 18 precision 4x4 MIMO 20-50 MHz, 5 carrier 18 x 18 → 27 x 27 precision 10 Mbps 100 Mbps 1,000 Mbps DSP performance  200X (multiple carriers, multiple antennae)

  7. Military Radar Up to Floating-Point Precision Limited Target Detection Ground mapping and see-thru wall radars • Simultaneous multiple target detection • 1000s of transmit-receive modules • 100s of sub-channels 18x18 precision DSP performance → 100X (multiple targets and transmit-receive modules)

  8. Today’s FPGA DSP Technology Does NOT Scale 9-bit Precision Floating-Point Precision TERA FLOPs 100 GMAC/s Video Surveillance Broadcast Systems Wireless Basestations Medical Imaging Military Radar High-Performance Computing Fixed-precision DSP architecture can not meet increasing performance needs within cost and power budgets

  9. Industry’s First Variable-Precision DSP Block Set the precision dial to match your application

  10. New Levels of DSP FPGA Performance High-Precision Mode 18-bit Precision Mode 1,840 GMACS or 1,000 GFLOPS performance in a single device

  11. Variable-Precision DSP AdvantagePrice and Power ⅓ DSP Resources ½ DSP Resources ½ DSP Resources Fixed Precision Fixed Precision Fixed Precision Variable Precision Variable Precision Variable Precision Military Radar Video Processing Wireless Basestations

  12. Total DSP Portfolio DSP Builder Timing-Driven Simulink Synthesis DSP Block Architecture Total DSP Solutions Video Design Framework Comprehensive Floating-Point IP

  13. Altera Video Design Framework IP Building Blocks Pre-Verified Video Reference Designs Video Kit Portfolio Building Blocks Video Streaming Interface Higher designer productivity = Faster time to market

  14. Altera Video Design FrameworkCustomer Application Video Mixer Color Space Conversion Motion-Adaptive Deinterlacing Clipping Scaling Video 1 Video Wall Color Space Conversion + CRS CRS and Color Space Conversion Clipping Scaling Video 2 Color Space Conversion + CRS Motion-Adaptive Deinterlacing Clipping CRS and Color Space Conversion Video 3 Composite Image Test Pattern Generation Proprietary Video Processing Video 4 Altera Video Framework Function Over 100 active customers to date Image: Apantac LLC. 14

  15. DSP Builder Advanced Blockset (DSPB-AB) HDL automatically optimized for system clock frequency and latency

  16. Altera’s Floating-Point Portfolio Largest portfolio of floating-point cores FFT MegaCore offers floating-point option Sine and cosine: Expected in Quartus software v.10.1

  17. Replacing Floating-Point Digital Signal Processors in Radar Systems Industry’s highest floating-point processing at the lowest power * 32 floating-point digital signal processors—2.7 GFLOP/s , 4 W each 17

  18. Replacing Multicore Digital Signal Processors in a LTE Channel Card 18

  19. Choice of LTE Towards a FPGA-Centric Architecture DSP Centric FPGA Centric

  20. Replacing ASSPs and Digital Signal Processors in High-End Conferencing Systems Video Design Framework Performance System Costs

  21. Expanding bandwidth demands driving need for increased processing performance Fixed-precision DSP blocks cannot meet increasing performance needs within cost and power budgets Altera is offering industry’s first variable-precision DSP block Altera’s DSP solution is replacing digital signal processors and ASSPs Summary

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