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FinFET

FinFET. Qin Zhang EE 666 04/19/2005. Outline. Introduction Design Fabrication Performance Summary. Introduction. Double-gate FET (DGFET) can reduce Short Channel Effects (SCEs) Reduce Drain-Induced-Barrier-Lowering Improve Subthreshold Swing S.

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FinFET

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  1. FinFET Qin Zhang EE 666 04/19/2005

  2. Outline • Introduction • Design • Fabrication • Performance • Summary

  3. Introduction Double-gate FET (DGFET) can reduce Short Channel Effects (SCEs) • Reduce Drain-Induced-Barrier-Lowering • Improve Subthreshold Swing S Medici-predicted DIBL and subthreshold swing versus effective channel length for DG and bulk-silicon nFETs E J Nowak, I Aller, T Ludwig, K Kim R V Joshi, C-T Chuang, K Bernstein and R Puri, IEEE Circuits and Dev. Magazine, p20-31, Jan/Feb 2004

  4. Introduction Three Types of Double-gate FET Quasi-COMS structure Relatively simple FAB J Kretz, L Dreeskornfeld, J Hartwich, and W Rosner, Microelectronic Eng. 67-68, p763-768, 2003

  5. Introduction First FinFET - DELTA (DEpleted Lean-channel TrAnsistor) D.Hisamoto, T.Kaga, Y.Kawamoto, and E.Takeda, IEEE Electron Dev. Lett., vol.11, no.1, p36-38, Jan 1990

  6. Design - Geometry Hfin >> Tfin Top gate oxide thickness >> sidewall oxide thickness Effective channel length Leff = Lgate + 2×Lext Effective channel width W = Tfin + 2×Hfin H -J L Gossmann, et al., IEEE Trans on Nanotechnology, vol.2, no.4, p 285-290, 2003 Gen Pei, et al., IEEE Trans on Electron Dev., vol.49, no.8, p1411-1419, 2002

  7. Design - Dependence of Vth and S Swing on Hfin • The saturation of Vth roll-off and S is observed when Hfin is increased from 20 nm to 90 nm • The critical Hfin needed for saturation is dependent on Tfin • For larger Tfin, the critical Hfin is correspondingly larger Gen Pei, et al., IEEE Trans on Electron Dev., vol.49, no.8, p1411-1419, 2002

  8. Design - Dependence of Vth and S Swing on Tfin • Vth roll-off and S change more and more rapidly as Tfin changing • from 10 nm to 60 nm, and slow down after that • Fin thickness reduce can suppress short channel effects, but the • variation will change the performance of the device a lot Gen Pei, et al., IEEE Trans on Electron Dev., vol.49, no.8, p1411-1419, 2002

  9. Design - SCEs with Leff/Tfin Leff/Tfin > 1.5 is desirable Kidong Kim, et al., Japanese J of Appl. Phys., vol.43, no.6B, p3784-3789, 2004

  10. Design - Other Optimization • Nonrectangular Fin • Hydrogen annealing to round off the corners • Source-Drain Fin-Extension Doping • Tradeoff regarding SCEs and S/D series resistance • Dielectric Thickness Scaling • Threshold Voltage Control • Channel doping with symmetric poly-Si gate • Asymmetric poly-Si gate • Metal gate Xusheng Wu, IEEE Trans on Electron Dev., vol.52, no.1, p63-68, 2005 Weize Xiong, et al., IEEE Electron Dev. Lett., vol.25, no.8, p541-543, 2004 Vishal Trivedi, IEEE Trans on Electron Dev., vol.52, no.1, p56-62, 2005 Jakub Kedzierski, et al., IEEE Trans on Electron Dev., vol.51, no.12, p2115-2120, 2004

  11. Fabrication 6.5 nm Si fin by Berkeley Team ---- Smallest in 2002 Poly-Si Si fin Yang-Kyu Choi et al., Solid-State Electronics 46, p1595-1601, 2002

  12. Fabrication - Spacer Lithography The thickness of spacer at the sidewalls determines the fin thickness Alternative: Electron Beam Lithography (20nm gate length and 15nm fin thickness was achieved) Yang-Kyu Choi et al., Solid-State Electronics 46, p1595-1601, 2002 W Rosner, et al., Solid-State Electronics 48, p1819-1823, 2004

  13. Fabrication - Process Flow “Easy in concept----Tough to build” (a) SiN is deposited as a hard mask, SiO2 cap is used to relieve the stress. (b) Si fin is patterned (c) A thin sacrificial SiO2 is grown (d) The sacrificial oxide is stripped completely to remove etch damage (e) Gate oxide is grown (f) Poly-Si gate is formed 10 nm gate length, 12 nm fin width Chenming Hu, et al. Dept. of EECS, UC-Berkeley, IEDM, p251-254, 2002

  14. Performance Chenming Hu, et al. Dept. of EECS, UC-Berkeley, IEDM, p251-254, 2002

  15. Performance - IV Characteristics • The drive currents are 446 uA/um for n-FinFET and 356 uA/um for • p-FinFET respectively • The peak transconductance of the p-FinFET is very high (633uS/um at • 105 nm Lg), because the hole mobility in the (110) channel is enhanced Chenming Hu, et al. Dept. of EECS, UC-Berkeley, IEDM, p251-254, 2002

  16. Performance - Speed and Leakage • Gate Delay is 0.34 ps for n-FET and 0.43 ps for p-FET respectively at 10 nm Lg • Gate leakage current is comparable to planar FET with the same gate oxide thickness Chenming Hu, et al. Dept. of EECS, UC-Berkeley, IEDM, p251-254, 2002

  17. Performance - Short Channel Effects Medici-predicted DIBL and subthreshold swing versus effective channel length for DG and bulk-silicon nFETs • The subthreshold slope is 125 mV/dec for n-FET and 101 mV/dec for p-FET respectively • The DIBL is 71 mV/V n-FET and 120 mV/V for p-FET respectively Chenming Hu, et al. Dept. of EECS, UC-Berkeley, IEDM, p251-254, 2002

  18. Summary “Easy in concept----Tough to build” • Double-gate FET can reduce Short Channel Effects and FinFET is the leading DGFET • Optimization design includes geometry, S-D fin-extension doping, dielectric thickness scaling, threshold voltage control…. • Fabrication of FinFET is compatible with CMOS process • 10 nm gate length, 12 nm fin width device has been fabricated and shows good performance

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