Julio C. G. Pimentel (pimentel@ieee) Hoang Le-Huy (lehuy@gel.ulaval)

1. An FPGA-Based Real Time Power System Simulator for Power Electronics Julio C. G. Pimentel (pimentel@ieee.org) Hoang Le-Huy (lehuy@gel.ulaval.ca) Gilbert Sybille (gsybille@ireq.ca) LEEPCI - Laboratory of Electro-technology, Power Electronics and Industrial Control Pimentel

2. Plan • Introduction • Proposed Approach • Implementation Flow • Library of Components • Experimental Results • Conclusion Pimentel

3. Introduction

4. Applications • Power system stability analysis • High frequency switched converters • High frequency motion control applications: • Industrial machines • Hybrid vehicles • Many more … Pimentel

5. Evolution of Real Time Power System Simulators Transient Network Analyzers (1970) Digital Computers (1990) Proposed Approach • Hardware Emulation • FPGAs + VHDL • DSP or mProcessor • Continue Time Models • Amplifiers and passive devices • Reduced scale models • Discrete Time Models • Parallel processors • Matrix Representation • Interactive Numeric Methods (algorithm) Hybrids Pimentel

6. Proposed Approach

7. General Architecture • Decouple the electrical network in two parts: • Linear part - RLC network is modelled as a matrix and processed by a microprocessor • Nonlinear part – nonlinear devices are modelled as VHDL sub-circuits and processed in the FPGA • Voltage and currents calculated by each part are exchanged at the end of each time step Pimentel

8. Data Flow Processing Model • The sub-circuits are interconnected through their input and output ports • The inputs of a sub-circuit can only change at the end of a time step • The outputs of a sub-circuit only depends on its inputs • At the end of a time step the sub-circuit transfers its calculated voltages and currents to the next sub-circuit • The sub-circuits are modelled in VHDL and implemented in a FPGA Pimentel

9. The synchronization Problem • The sub-circuits I/O signals can be: • Control signals: CLK, RST, EN, STC, EOC and REG • Voltages and currents – fixed point integer • Logical signals: carry On/OFF information (PWM outputs, RST EN STC EOC Reg CLK Sub Circuit Voltages Voltages Currents Currents Logical Signals Logical Signals Pimentel

10. The synchronization Problem (cnt’d) • The control signals are: • Generated by a master state machine that synchronizes the whole system • Sent to all VHDL sub-circuits • The SM controls: • Initialization - Stability depends a lot on the initialization strategy • Sequencing • Send data to/from DAC • Send data to/from uP • Process data EOC1 EOC2 EOCn EN Master State Machine STC_l STC_nl REG_l REG_nl RST CLK Pimentel

11. Z-1 Vb(t-1) I(t-1) Z-1 Decoupling Strategy • Decouple the linear and nonlinear parts by introducing a Voltage-Current pair => reduce the size of the problem • Problem: the value of I et Vb used in each part are delayed by one time step => system may become unstable ? Pimentel

12. Decoupling Strategy (cnt’d) ? Pimentel

13. Decoupling Strategy (in parallel) Sources Nonlinear Diode, Thyristor, MOSFET, Control, etc. AC, DC, Sin, Pulse, Step, etc. VHDL Z-1 Z-1 ALGORITHM State Space Model [A, B, C, D] linear Total: 2 time step delay Pimentel

14. Decoupling Strategy (in series) The simulation of the nonlinear part takes much less than 1 us Sources Nonlinear Diode, Thyristor, MOSFET, Control, etc. AC, DC, Pulse, Step, etc. VHDL Zero Delay Z-1 ALGORITHM State Space Model [A, B, C, D] linear Total: ONLY 1 time step delay (more stable) Pimentel

15. Implementation Flow

16. Implementation Flow PSB/Matlab Schematic Library of Components For DRTPSS Translate PSB To VHDL Vendor Library Elaboration DRTPSS Simulator FPGA Design Flow Synthesis Placement Routing FPGA Programming Pimentel

17. Library of parameter-driven components Sources: DC, ramp, sinus, etc. 1f and 3f PWM modulators PI and PID controllers DQ-ABC and ABC-DQ converters Components (diode, MOST, Thyristor, etc.) Digital filters and CORDIC D/A converters

18. n, nc, VMax Sin_1Ø clk n n out Freq en clock Sinusoidal source • The sinusoidal source (example): • Can generate a sinus with 16-bit resolution (amplitude and phase) • Approximation: series of Taylor (can also use a lookup table): • Implemented using multiply-accumulate operations • Distortion < 1% Pimentel

19. n n input out PWM_1Ø enable en load ld clock clk PWM Modulator • The PWM modulator (example) • Resolution: ex.: 8 bits • frequency: 2.99 Mhz • Modulation factor: 25% Pimentel

20. n, nc, VMax Sin_3Ø n n Freq out_A n out_B n en out_C clock clk State machine n D Q PWM_1Ø EN out_A En C Ld R clk clk n D Q PWM_1Ø EN out_B En C Ld R clk Sin_1Ø n n n D Q PWM_1Ø Freq EN out_C En C clk R Ld clk clock 3f sinusoidal PWM Modulator Pimentel

21. Experimental Results

22. Ex1: Full Wave Rectifier FPGASim • FPGASim – proposed simulator (real time simulator) • PSB – Power System Blockset of Matlab (non real time simulator) PSB Pimentel

23. Ex2: Thyristor Rectifier FPGASim PSB Pimentel

24. Ex3: Effect of Transitory on a DC-DC Buck Converter FPGASim PSB Pimentel

25. Ex4: DC-DC Buck Converter with PI Controller Kp=0.1 Ki=4 FPGASim L1=20mH R=20 C=30uF PSB Pimentel

26. Ex5: Three-phase DC-AC PWM Converter FPGASim PSB Pimentel

27. Ex6: 50Hz – 60Hz Cicloconverter FPGASim Vpeak=150V Ls=100uH Rl=10Ohm Ll=100mH Vc=100uF PSB Pimentel

28. Conclusion

29. Device RocketIO Transceiver Blocks PowerPC Processor Blocks Logic Cells(1) CLB (1 = 4 slices = max 128 bits) 18 X 18 Bit Multiplier Blocks Block SelectRAM+ DCMs Maximum User I/O Pads Slices Max Distr RAM (Kb) 18 Kb Blocks Max Block RAM (Kb) XC2VP2 4 0 3,168 1,408 44 12 12 216 4 204 XC2VP4 4 1 6,768 3,008 94 28 28 504 4 348 XC2VP7 8 1 11,088 4,928 154 44 44 792 4 396 XC2VP20 8 2 20,880 9,280 290 88 88 1,584 8 564 XC2VP30 8 2 30,816 13,696 428 136 136 2,448 8 644 XC2VP40 0(2), 8, or 12 2 43,632 19,392 606 192 192 3,456 8 804 XC2VP50 0(2)or 16 2 53,136 23,616 738 232 232 4,176 8 852 XC2VP70 16 or 20 2 74,448 33,088 1,034 328 328 5,904 8 996 XC2VP100 0(2)or 20 2 99,216 44,096 1,378 444 444 7,992 12 1,164 FPGA Used • Xilinx 2VP30 Virtex II PRO • Logic Cells (1): 30,816 • Slices: 13,696 • 18 X 18 Bit Multiplier Blocks: 136 • Maximum User I/O Pads: 644 • PowerPC Processor Blocks: 2 (1) Logic Cell = (1) 4-input LUT + (1)FF + Carry Logic Pimentel

30. Summary (nonlinear part only) NOTE: 1) implemented on a Xilinx 2VP30 Virtex II PRO FPGA 2) results taken after placement and routing Pimentel

31. Conclusion • Proposed a new approach to implement DRTPSSs based on programmable hardware and HDL languages • The proposed simulator produces results comparable to those obtained with the PSB/Matlab from Mathworks • The initial results show that the technique has the potential to create a breakthrough in DRTPSS and set a new level of performance for these simulation tools Pimentel