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Lecture 13. ES 210 Latches and Flip-Flops Jack Ou , Ph.D. Using a Latch as a Memory Element. Caution for a D latch: once a clock enables a D latch, the output changes as soon as the input changes – this is not desirable if you do not
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Lecture 13 ES 210 Latches and Flip-Flops Jack Ou, Ph.D.
Using a Latch as a Memory Element Caution for a D latch: once a clock enables a D latch, the output changes as soon as the input changes – this is not desirable if you do not want the output to change continuously and all the latches use a common clock.
Negative Edge triggered D Flip-FlopClk=0 Q=Y hold 0 1
Negative Edge triggered D Flip-FlopClk=1 Y=D hold 1 0
Negative Edge Triggered D Flip-Flop 2 1 The value that is produced at the output of the flip-flop is the value that was stored in master stage immediately before the negative edge Occurred. OUT=X Not enough time for D→Y→Q Q will hold steady Y=D 1: Track 1:hold 1:hold CK of latch 1 CK of latch 2 2: Hold 2:track 2:track Q=Y
Positive Edge D-Flop X 2 1 OUT=X 2: Track 2:hold 2:hold CK of latch 2 CK of latch 1 1: Hold 1:track 1:track X=IN
Definition • Setup time: the time that the incoming data must be stable before the clock arrives • Hold time: the length of time that the data remains stable after the clock arrives for proper operation • If the data is stable before the setup time and continues to be stable after the hold time, the flop will work properly. • If the data arrives within the period designated by the setup and hold times, the flop may or may not capture the correct value.
CLK-Q • The delay from the time that the clock arrives to the point that the output stabilizes. • In reality the data must arrive at the setup time before the clock hits and the output is valid after the CLK-Q delay.
Question • How would you change a negative edge triggered flip-flop to a positively edge triggered flip-flop?
D-Type Positive Edge Triggered Flip-Flop (CLK=0) 1 0 1 0 CLK =0, maintain the present state
D-Type Positive Edge Triggered Flip-Flop D=0 as Clk=0→ 1 1 0 1 0→1 1 → 0 0 1 Q changes 0
D-Type Positive Edge Triggered Flip-Flop D=1 as Clk=0→ 1 0 1 1 → 0 0→1 1→ 1 1 0 Q changes 1
D-Type Positive Edge Triggered Flip-Flop D=0→ 1 as Clk=1 1 S’ S 1 S’ The flip-flop is unresponsive to changes in D 0 → 1 1 Please explore different possible value of S on your own. This will work even for S=R=1 and S=R=0.
reset and preset • When power is first turned on, the state of the flip-flops is unknwon. • Reset is used to initialize the output to a 0. • Preset is used to initialize the output to a 1.
Reset Feature 1 0 1 1 0
D Flip-flop with reset Typo in the book. Should be 1 instead.
JK Flip-Flops D=JQ’+K’Q Positive edge D flip-flop The next value of D is determined by JQ’+KQ. At the rising edge of D Flip-flop, Q is updated with the value of D.
D=JQ’+K’Q • J=1,K=1→D=Q’ • J=0, K=0→D=Q • J=0, K=1→D=0 • J=1, K=0→D=Q’+Q=1
T Flip-Flop from D Flip-Flop D=TQ’+T’Q If T=1, D=Q’ If T=0, D=Q. Q is updated with D at the next rising edge.
