CSCE 932, Spring 2007

1. CSCE 932, Spring 2007 Fault Coverage Analysis

2. Fault Simulation

3. Problem and Motivation • Problem: Given • A circuit • A sequence of test vectors • A fault model • Determine • Fault coverage - fraction (or percentage) of modeled faults detected by test vectors • Set of undetected faults • Motivation • Determine test quality and in turn product quality • Find undetected faults as targets for test generation to improve coverage

4. Verification input stimuli Verified design netlist Fault simulator Test vectors Modeled fault list Test compactor Remove tested faults Delete vectors Low Fault coverage ? Test generator Add vectors Adequate (Courtesy: Dr. V. D. Agrawal) Stop Multiple Roles of a Fault Simulator in the Design Process

5. Modeling Issues in Fault Simulation • Circuit model: mixed-level • Mostly logic with some switch-level for high-impedance (Z) and bidirectional signals • High-level models (memory, etc.) with pin faults • Signal states: logic • Two (0, 1) or three (0, 1, X) states for purely Boolean logic circuits • Four states (0, 1, X, Z) for sequential MOS circuits • Timing: • Zero-delay for combinational and synchronous circuits • Mostly unit-delay for circuits with feedback

6. Modeling Issues in Fault Simulation (Continued) • Faults: • Mostly single stuck-at faults • Sometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in common use • Equivalence fault collapsing of single stuck-at faults • Fault-dropping -- a fault once detected is dropped from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosis • Fault sampling -- a random sample of faults is simulated when the circuit is large

7. Total Computational Task in Fault Simulation Note: The variance of the total machine state is much smaller down a column vs. across a row. This observation is the basis for efficient fault simulation algorithms.

8. 0 0 0 0 0 1 1 0 1 1 1 0 M1 0 0 1 0 1 1 1 1 0 1 1 1 1 0 0 1 1 1 1 1 0 0 1 0 0 0 x 0 0 1 0 0 0 1 x 0 0 1 1 0 1 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 x 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 0 0 1 1 x M2 Example: Fault Simulation of the Good and Two Faulty Machines M0 0 1 0 1 0 x 0 1 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 1 1 x 1 x 0 1 0 1 1 1

9. Fault Simulation Algorithms • Serial • Concurrent • Differential • Parallel • Deductive

10. Serial Fault Simulation The algorithm carries out the computational task row-by-row, from left to right

11. Serial Fault Simulation Algorithm • Simulate fault-free circuit and save responses. • Repeat the following steps for each fault in the fault list: • Modify netlist by injecting one fault • Simulate modified netlist, vector by vector, comparing responses with saved responses • If response differs, report fault detection and suspend simulation of remaining vectors (fault dropping) • Advantages: • Easy to implement; needs only a true-value simulator, less memory • Most faults, including analog faults, can be simulated • Disadvantage: • Much repeated computation; CPU time prohibitive for VLSI circuits

12. Test vectors Fault-free circuit Comparator f1 detected? Circuit with fault f1 Comparator f2 detected? Circuit with fault f2 Comparator fn detected? Circuit with fault fn Serial Algorithm: Graphical View

13. M0 0 1 0 1 0 x 0 1 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 1 1 x 1 x 0 1 0 1 1 1 0 0 0 0 0 1 1 0 1 1 1 0 M1 * * * 0 * * * 0 1 0 1 * * * 1 1 1 0 1 1 1 1 0 0 1 1 1 1 1 0 0 1 0 0 0 x 0 0 1 0 0 0 1 M2 x 0 0 1 1 0 1 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 x 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 0 0 1 1 x * * * * * * Event-driven Gate Evaluations in the Example Serial Simulation * * * * * * * * * * * *

14. Concurrent Fault Simulation [UB74] • Event-driven simulation of fault-free circuit and only those parts of the faulty circuit that differ in signal states from the fault-free circuit. • A list per gate containing copies of the gate from all faulty circuits in which this gate differs. List element contains fault ID, gate input and output values and internal states, if any. • All events of fault-free and all faulty circuits are implicitly simulated. • Faults can be simulated in any modeling style or detail supported in true-value simulation (offers most flexibility.) • Faster than other methods, but uses most memory.

15. Concurrent Fault Simulation (Cont.) The algorithm carries out the computational task column-by-column from left to right, all the machines in a column are processed concurrently.

16. M0 0 1 0 1 0 x 0 1 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 1 1 x 1 x 0 1 0 1 1 1 0 0 0 0 0 1 1 0 1 1 1 0 M1 * * 0 0 1 0 1 1 1 1 0 1 1 1 1 0 M2 0 1 1 1 1 1 0 0 1 0 0 0 x 0 0 1 0 0 0 1 x 0 0 1 1 0 1 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 x 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 0 0 1 1 x * * * * Concurrent Fault Simulation: Example * * * * * * * * * *

17. Differential Fault Simulation [CY90] • Similar to concurrent, except, rows in a column are processed sequentially, not concurrently. • The faulty machine Mk+1(i+1) is constructed by taking the difference in the total state from the immediately preceding machine Mk(i+1) in the same column. • Advantage: Avoids the dynamic memory management of faulty gate lists in concurrent fault simulation. • Disadvantage: Fault dropping and detection are more complicated, requiring more computation.

19. M0 0 1 0 1 0 x 0 1 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 1 1 x 1 x 0 1 0 1 1 1 0 0 0 0 0 1 1 0 1 1 1 0 M1 * * 0 0 1 0 1 1 1 1 0 1 1 1 1 0 0 1 1 1 1 1 0 0 1 0 0 0 x 0 0 1 0 0 0 1 x 0 M2 0 1 1 0 1 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 x 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 0 0 1 1 x * * * * * Differential Fault Simulation: Example * * * * * * * * * * * * *

20. Fault Sampling

21. Fault Sampling • A randomly selected subset (sample) of faults is simulated. • Measured coverage in the sample is used to estimate fault coverage in the entire circuit. • Advantage: Saving in computing resources (CPU time and memory.) • Disadvantage: Limited data on undetected faults.

22. Motivation for Sampling • Complexity of fault simulation depends on: • Number of gates • Number of faults • Number of vectors • Complexity of fault simulation with fault sampling depends on: • Number of gates • Number of vectors

23. Random Sampling Model Detected fault Undetected fault All faults with a fixed but unknown coverage Random picking Np = total number of faults (population size) C = fault coverage (unknown) Ns = sample size Ns << Np c = sample coverage (a random variable)

24. Probability Density of Sample Coverage, C C (1 - C) Variance, s 2 = ------------ Ns Sampling error s s p (x ) Mean = C x 1.0 C +3s C -3s x C Sample coverage

25. Sampling Error Bounds Solving the quadratic equation for C, we get the 3-sigma (99.7% confidence) estimate: Where Ns is sample size and x is the measured fault coverage in the sample. Example: A circuit with 39,096 faults has an actual fault coverage of 87.1%. The measured coverage in a random sample of 1,000 faults is 88.7%. The above formula gives an estimate of 88.7% 3%. CPU time for sample simulation was about 10% of that for all faults.

26. Summary • Fault simulator is an essential tool for test development. • Concurrent fault simulation algorithm offers the best choice. • For restricted class of circuits (combinational and synchronous sequential with only Boolean primitives), differential algorithm can provide better speed and memory efficiency (Section 5.5.6.) • For large circuits, the accuracy of random fault sampling only depends on the sample size (1,000 to 2,000 faults) and not on the circuit size. The method has significant advantages in reducing CPU time and memory needs of the simulator.

27. References

28. 1.[AMM84] Critical Path Tracing: An Alternative to Fault Simulation Miron Abramovici, Prem R. Menon, and David T. Miller IEEE Design & Test of Computers Volume 1 ,  Issue 1, Feb. 1984, Pages: 83 - 93 , Abstract: 2.[AKP+90] Why is Less Information From Logic Simulation More Useful in Fault Simulation? Sheldon B. Akers, Balakrishnan Krishnamurthy, Sungju Park, and Ashok Swaminathan Test Conference, 1990. Proceedings., InternationalSept. 1990, pages: 786 - 800 Abstract: The authors propose a novel linear-time algorithm for identifying, in a large combinatorial circuit, a large set of faults that are undetectable by a given test vector. Although this so-called X-algorithm does not identify all the undetectable faults, empirical evidence is offered to show that the reduction in the number of remaining faults to be simulated is significant. The algorithm is intended as a simple, fast preprocessing step to be performed after a test vector has been generated, but before the (often lengthy) process of fault simulation begins. The empirical results indicate that the X-algorithm is both useful (indicated by the utility factor) and good (indicated by the effectiveness factor). It provides as much as a 50% reduction in the number of faults that need to be simulated. Moreover, the algorithm seems to identify a large fraction of the undetectable faults

29. 3.[MLA91] SCRIPT: a critical path tracing algorithm for synchronous sequential circuits Menon, P.; Levendel, Y.; Abramovici, M. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume: 10  Issue: 6  Jun 1991, Page(s): 738-747, Abstract: The basic critical path tracing method for combinational circuits is outlined, and it is shown how it can produce pessimistic results in certain cases where fault effects propagate along multiple paths. The problem of extending the critical path trac..... 4.[CY90] Differential Fault Simulation for Sequential Circuits Wu-Tung Cheng and Meng-Lin Yu Journal of Electronic Testing: Theory and Applications Volume 1 ,  Issue 1, February 1990, Pages: 7 - 13 , Abstract: A new fast fault simulation algorithm called differential fault simulation, DSIM, for synchronous sequential circuits is described. Unlike concurrent fault simulation, for every test vector, DSIM simulates the good machine and each faulty machine separately, one after another, rather than simultaneously simulating all machines. Therefore, DSIM dramatically reduces the memory requirement and the overhead in the memory management in concurrent fault simulation. Also, unlike serial fault simulation, DSIM simulates each machine by reprocessing its differences from the previously simulated machine. In this manner, DSIM is more efficient than serial fault simulation. Experiments have shown that DSIM runs 3 to 12 times faster than an existing concurrent fault simulator. In addition, owing to the simplicity of this algorithm, DSIM is very easy to implement and maintain. An implementation consists of only about 300 lines of C language statements added to the event-driven true-value simulator in an existing sequential circuit test generator program, STG3. Currently DSIM uses the zero-delay timing model. The addition of alternative delay models is under development.

30. 5.[CGR91] Fast Differential Fault Simulation by Dynamic Fault Ordering G. Cabodi, S. Gai, and M. Sonza Riorda Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings., 1991 IEEE International Conference on Oct. 1991, pages: 60 - 63 Abstract: A technique that makes it possible to significantly improve the effectiveness of the differential algorithm for the fault simulation of synchronous sequential circuits is presented. The approach is based on dynamically reordering the fault list before the simulation of each input pattern: faults not yet detected are grouped according to a strategy aiming at minimizing the status differences between successive faults. In such a way the activity to be processed while computing each faulty circuit is minimized at a quite low computational cost. Experimental results are provided showing the effectiveness of the proposed method 6.[UB74] The Concurrent Simulation of Nearly Identical Digital Networks E. G. Ulrich and T. Baker IEEE Computer, Vol. 7, April 1974, pages: 39-44

31. 7.[ASA82] Fault coverage requirement in production testing of LSI circuits Agrawal, V.D.; Seth, S.C.; Agrawal, P. Solid-State Circuits, IEEE Journal of, Volume 17, Issue 1, Feb 1982 Page(s):57 - 61 Abstract: A technique is described for evaluating the effectiveness of production tests for large scale integrated (LSI) circuit chips. It is based on a model for the distribution of faults on a chip. The model requires two parameters, the average number (n/SUB 0/) of faults on a faulty chip and the yield (y) of good chips. It is assumed that the yield either is known or can be calculated from the available formulas. The other parameter, n/SUB 0/, is determined from an experimental procedure. Once the model is fully characterized, it allows calculation of the field reject rate as a function of the fault coverage. The technique implicitly takes into account such variables as fault simulator characteristics, the feature size, and the manufacturing environment. An actual LSI circuit is used as an example.