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Nortel Networks Institute University of Waterloo

Nortel Networks Institute University of Waterloo. Embedded SRAM Design Challenges for Nano-metric Technologies. Manoj Sachdev Electrical and Computer Engineering msachdev@ece.uwaterloo.ca. Talk Outline. Group Introduction Motivation SRAM Basics Low Power Techniques Data Stability

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Nortel Networks Institute University of Waterloo

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  1. Nortel Networks InstituteUniversity of Waterloo CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  2. Embedded SRAM Design Challenges for Nano-metric Technologies Manoj Sachdev Electrical and Computer Engineering msachdev@ece.uwaterloo.ca

  3. Talk Outline • Group Introduction • Motivation • SRAM Basics • Low Power Techniques • Data Stability • Soft Errors • Conclusions CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  4. Group Introduction • 6 PhD, 3 masters, 2 PDFs • Applied, industrially driven research • Generous funding levels • Core strengths in circuit design, testing, quality and reliability http://www.ece.uwaterloo.ca/~cdr CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  5. Group: Low Power Research • Driven by low power signal processing & bio-implantable applications • Research focus • Active power reduction, clocking strategies • Dynamic voltage scaling architecture for portable app. • Leakage power reduction • Investigation of RBB effectiveness with scaling CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  6. Group: High Performance Circuits • Driven by high speed arithmetic circuits (Adders, registers files, ALU), and CDRs • Research focus • Building timing diagnostics into multi-GHz ALUs • Leakage & active power reduction • Clock de-skewing • Thermal issues in high performance circuits CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  7. Group: Memory Research • Driven by embedded SRAMs and CAMs • Research Focus • SRAM cell stability, circuit techniques for detection • Low power SRAM architectures • Sense amplifiers • Soft error robust SRAM and flip-flop design • Leakage reduction, matchline sensing tech., high speed PE design, and test issues in CAMs CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  8. Talk Outline • Group Introduction • Motivation • SRAM Basics • Low Power Architectures • Data Stability • Soft Errors • Conclusions CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  9. Why SRAM? • SRAM occupies majority of SoC die area • Increasing transistor count • Contributes to leakage and active power • Limits SoC yield, testability & reliability 65nm Dual Core Xeon die CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  10. Source: IBM Research Source: Magma Design Automation Nano-metric Design Hurdles • Increased process variability • Wider variations in Ileak, Ion, delay etc. due to intra and inter die variations in VTH, Leff, Weff CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  11. 6T cell Nominal Vdd Nano-metric SRAM Design Challenges • Millions of leaking transistors • Lower battery life • Process variation • Poorer data stability • Data retention faults • Smaller transistors • Increased soft error rate Pilo et al., JSSC, p. 813, Apr. 2007 CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  12. Talk Outline • Group Introduction • Motivation • SRAM Basics • Low Power Architectures • Data Stability • Soft Errors • Conclusions CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  13. SRAM Architecture CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  14. SRAM Cell • Cell design objectives • Non destructive read • Wdriver = (1.5 ~ 3)Waccess • cell ratio • Can be written into k’n(W/L)access = (2~3)k’p(W/L)load • Design tradeoffs • Area, speed, power = f (cell ratio) • SNM = f (cell ratio)  area, speed, power • Effect of Scaling • Supply voltage scaling  SNM • Process spread cell asymmetry  SNM CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  15. SRAM Static Noise Margin Seevink (JSSC ’87) CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  16. SRAM SNM: Read Access • Worst case SNM – in read-accessed mode • Logic “zero” is degraded by an access transistor CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  17. Talk Outline • Group Introduction • Motivation • SRAM Basics • Low Power Architectures • Data Stability • Soft Errors • Conclusions CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  18. Power Struggle: Leakage Tj = 25°C Source: IBM CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  19. 10 1.2 Berkeley Predictive Tech. Models 1 High VTH 0.8 0.1 Normalized ION/IOFF (n-MOS transistor) Normalized threshold voltage Low VTH 0.4 0.01 ION/IOFF ratio degradation: ~26x 0 40 70 100 130 Technology generation (nm) Sub-130nm Scaling Trends • VTH scaled for performance, ION(VDD-VTH) • IOFF/ µm↑3-5x/generation: result ION/IOFF degradation CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  20. Transistor Leakage Current Model Threshold voltage impact DIBL impact Body bias impact VGS = 0 when transistor is off 1 when VDS = VDD CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  21. 1.2 70nm, 1100C, typical corner ref. pt. (no leakage ctrl.) 0.9 OFF VDD scaling 0.6 Normalized I 4.5x non-min. Le 0.3 stack effect RBB -12% 0 1.1 1 0.9 0.8 0.7 0.6 0.5 Normalized I ON Leakage Control: ION-IOFF Tradeoffs Max. ION degradation Source – Chatterjee, Sachdev et. al, VLSI Sym. 03 • RBB, non-min. Le “steepest” gradient in ION-IOFF plane CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  22. Row based Low-power SRAM Architectures • Kanda & Sakurai (JSSC’04) • Saves Write Power • Turn-off the SLC switch before write • Limited swing on BL • For read • Turn-on the SLC switch to drive the BL CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  23. Row based Architectures - Issues • Unrealistic approach for multi-word/row case • Write operation would be destructive to all cells in one row • Higher power in read operation Kanda et. al., JSSC, p.927, June 2004 CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  24. Column Based Low-power SRAM Architecture • Four distinct operational modes 1. Retention 2. Read 3. Accessed Retention 4. Write • Desirable features • Low-leakage • Low-write power • Higher write margin • Non-selected words do not discharge BLs • Lower read power • Minor speed trade-off Sharifkhani & Sachdev, TVLSI, p. 196, Feb. 2007 CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  25. Retention Mode • Array is in hibernation VH – VL = 0.4V • No multiple VTs! • Body effect minimizes leakage • Potential issue: data stability • weak drive transistors CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  26. Read Mode • Multiple words/row • Only selected word enters this mode • SVG becomes VSS • bitline discharges via access & driver transistors • Good data stability • voltage across cell ≈ VH • VB-VA > VH-VL CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  27. Accessed Retention Mode • Non-selected words (BLs) on selected row enters this mode • high VWL • no SVG variation • no bitline discharge • Minimum access leakage • Issue: data stability • VWL= VH+Vtha-VΔ • VΔ>200mV • recovery after access CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  28. Write Mode • Low BL voltage swing • VWR Sufficiently below VH-VΔ • VWR= VL • BL swing, DVBL ≈ 400 mV • Low power consumption • Pwrite∝ VH. DVBL • no SVG variation CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  29. SVGND Architecture Sharifkhani & Sachdev, TVLSI, p. 196, Feb. 2007 CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  30. Column vs Row VGND • Column based scheme is superior • Smaller VSS switch: less area overhead • Larger drive current during read access • Higher operating frequency Sharifkhani & Sachdev, TVLSI, p. 196, Feb. 2007 Kanda et. al., JSSC, p.927, June 2004 CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  31. Talk Outline • Group Introduction • Motivation • SRAM Basics • Low Power Architectures • Data Stability • Soft Errors • Conclusions CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  32. SRAM SNM Sensitivity Analysis • SNM vs. VTH variation • SNM vs. Leff, Weff • SNM vs. VBL, VWL, VDD, T0C • SNM vs. non-catastrophic Rbridge and Rbreak • Multiple parameter variation can lead to much more dramatic decrease in SNM… CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  33. SNM vs. single VTH variation • Single transistor VTH variation • Typ. case  0% VTH deviation and 0% SNM deviation • Process corners: • slowtypfast • SNMSNMSNM • VTH_driver – strongest impact on SNM • VTH_access, VTH_load – moderate impact on SNM CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  34. SNM vs. multiple VTH variation • Multiple transistor VTH variation • One VTH is changing, other - biased • SNM degradation may become severe CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  35. SNM vs. VDD_CELL • VTCs of SRAM cell with reduced array supply (WL and BL voltages kept at VDD) CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  36. How to Test Stability Faults?? • Data Retention Faults  subset of Stability Faults • For high reliability products DRT (Delay Test) alone is not sufficient anymore DRF Stability faults CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  37. Stability Fault Modeling • Node A to node B resistive bridge • Provides negative feedback • Reduces the SNM by symmetrical reduction of the both inverter gains Pavlov, Sachdev & Pineda, pp. 1106-1115, ITC 2004 CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  38. Stability Fault Modeling • Node A to node B resistive bridge • SNM=linear function of Rnode A-node B from 50k to 500k • SNM range: 0%-80% • Worst case SNM • Worst case SNM ~15-30% of typical CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  39. Detection Techniques: Principle • Principle • apply stress such that “good” cells withstand it, whereas “weak” cells flip • @VTEST weak cell will flip, good cell will retain the data CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  40. Detection Techniques Passive Active (DFT) Fixed detection threshold Programmable detection threshold • DRT • LVT • HTT • WWTM • SDD • WL overdrive • etc. • PWWTM • RatioofIread’s • WL pulsing Stability Fault Detection: DFT CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  41. Detection: WL pulsing • Rweak=200k • Weak cell flips for number of WL_ref pulses>12 (red and violet lines)0 Pavlov, Sachdev & Pineda, pp. 2334-2343, JSSC Oct 06 CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  42. Talk Outline • Group Introduction • Motivation • SRAM Basics • Low Power Architectures • Data Stability • Soft Errors • Conclusions CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  43. Voltage + _ Time n+ - + - + 1 1 1 0 0 0 - + + - - + - + Soft Error (SE) G S V+ D n+ - - - Qcoll<Qcrit no error;Qcoll>Qcrit  soft error - + - + - + p substrate B ‘1’ ‘0’ or ‘0’ ‘1’ CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  44. Soft Error Sources • External • Alpha particles • Doubly ionized 4He2+ atom • Penetrates 25mm in Si, deposits 4-16 fC/mm • Sources: Pb in solder balls; U, Th in packaging materials • High energy neutrons • Comes from sun or inter-galactic rays • Deposits 4-16 fC/mm through Si recoil • Omnipresent, flux increases with elevation • Internal • Power/ground line noise • substrate noise • capacitive coupling External sources determine soft error rate in carefully designed systems CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  45. SE Susceptible Systems • Earlier, only space-borne and aircraft electronics was believed to be prone to SE • Now, all ground level electronics is vulnerable • Network servers and routers, memories, FPGA, life saving equipment like cardiac defibrillators, etc. CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  46. Sensitive node contact M1-M2 via diffusion I restore gate poly M1 M2 Sensitive node SE in SRAM • Particle strikes cause bit flip • No masking mechanism • Two sensitive nodes • Positive feedback aids bit flipping process • Critical charge: CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  47. Scaling and SRAM SER • System SER increases with scaling • Lower V & C reduces Qcrit; smaller volume reduces collected charge • Bit SER = constant; system SER = ↑ due to increased # of bits/chip • Low-power techniques further increase SER P. Dodd, et. al., IEDM’02, pp.333-336. R. Baumann, IEEE Design and Test of Computers, pp. 258-266, May-June 2005 CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  48. SE Mitigation • Layout level • Reduction of sensitive area, using extra doping layer (epitaxial layer can help) or SOI etc. • Circuit level • Circuit techniques to reduce sensitivity to transients • Architecture level • Parity protection (only error detection), Error Correction Code (ECC), Error Detection and Correction (EDAC) Code We consider circuit and architecture level techniques as the first one requires process modification CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  49. Circuit Level Mitigation T. M. Mnich, et. al., IEEE Trans. Nucl. Sci., p. 4620, 1983 Ootsuka et. al., IEDM 1998 Cypress Semiconductors P. Roche, et. al., IRPS 2004 CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

  50. Simulation results in 130nm technology Effectiveness of Circuit Tech. • Higher Qcrit, but not immune • Lower level of confidence • Exhibits significant area penalty • Immune cells require at least 10 transistors • 67% more array area • Larger WL and BL capacitance • higher power consumption Calin et. al., IEEE Trans. Nucl. Sci., p. 2874, Dec. 1996 CMOS Design and Reliability Group Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada – N2L 3G1

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