ECE 424 Design of Microprocessor-Based Systems

1. ECE 424 Design of Microprocessor-Based Systems Haibo Wang ECE Department Southern Illinois University Carbondale, IL 62901

2. Connections Between CPU and Memory Control signals Memory 8088 Data Bus Address bus • What are the control signals from the microprocessor to memory? What are the control signal from memory to the microprocessor? • Address and data signals should be buffered • The use of buffers on address bus increases driving capability • Bi-directional buffers are used to control the data transferring directions on data bus • D latches are used to de-multiplex signals on AD[7:0] (and A[19:16])

3. Timing Diagram of A Memory Operation • Example:8088 sends address 70C12 to memory in a memory read operation assume that data 30H is read T3 T4 T2 T1 CLK Addr[15:0] D latch ALE 8088 A[15:8] A[19:16] 7H S3-S6 Buffer A[15:8] 0CH AD[7:0] Memory D latch AD[7:0] 12H 30H D[7:0] Trans -ceiver Addr[19:16] 7H DT/R DEN Addr[15:8] 0CH IO/M Addr[7:0] 12H WR RD D[7:0] 30H

4. 256KB 256KB 256KB 256KB CS CS CS CS Addr[17:0] Addr[18] 2-to-4 decoder Addr[19] CS IO/M Memory Address Decoding • Design a 1MB memory system consisting of multiple memory chips • Solution 1:

5. 256KB 256KB 256KB 256KB CS CS CS CS Addr[19:2] Addr[1] 2-to-4 decoder Addr[0] CS IO/M Memory Address Decoding • Design a 1MB memory system consisting of multiple memory chips • Solution 2:

6. 256KB 256KB 256KB 256KB CS CS CS CS Addr[19:18] Addr[16:7] Addr[5:0] Addr[17] 2-to-4 decoder Addr[6] CS IO/M Memory Address Decoding • Design a 1MB memory system consisting of multiple memory chips • Solution 3: It is a bad design, but still works! Does it work if the last memory chip is removed?

7. Memory Address Decoding • Design a 1MB memory system consisting of multiple memory chips • Solution 4: 256KB 256KB 512KB CS CS CS Addr[17:0] Addr[18] Addr[18] Addr[19] IO/M Addr[19] Addr[18] Addr[19] IO/M IO/M

8. Addr[14:0] 32KB Addr[19] CS Addr[18] Addr[17] Addr[16] Addr[15] IO/M Memory Address Decoding • Using partial memory addressing space Addr[19:0] FFFFF 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Highest address 37FFF 32KB Lowest address 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30000 These 5 address lines are not changed. They set the base address These 15 address lines select one of the 215 (32768) locations inside the RAMs 00000 Can we design a decoder such that the first address of the 32KB memory is 37124H?

9. Memory Address Decoding • Exercise Problem: • A 64KB memory chip is used to build a memory system with the starting address of 7000H. A block of memory locations in the memory chip are damaged. FFFFH 7FFFFH 733FFH 3317H 73317H Replace this block 3210H 73210H 73200H 0000H 70000H 64KB Damaged block 1M addressing space 1M addressing space

10. A[19] A[18] A[17] CS A[16] IO/M A[15] A[14] A[13] A[12] CS A[11] A[10] A[9] Memory Address Decoding 64KB A[15:0] 512B A[8:0]

11. Memory Address Decoding • Exercise Problem: • A 2MB memory chip with a damaged block (from 0DCF12H to 103745H) is used to build a 1MB memory system for an 8088-based computer 1FFFFFH 1FFFFFH 512K 18FFFFH 103745H Use these two blocks 0FFFFFH 0DCF12H 07FFFFH 512K 000000H 000000H Damaged block A[19] A[20] A[19:0] A[19:0] CS

12. Memory Address Decoding • Partial decoding • Example: • build a 32KB memory system by using four 8KB memory chips • The starting address of the 32KB memory system is 30000H 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 high addr. of chip #4 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Low addr. of chip #4 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 high addr. of chip #3 Chip #4 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36000H Low addr. of chip #3 Chip #3 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 34000H high addr. of chip #2 Chip #2 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Low addr. of chip #2 32000H Chip #1 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 30000H high addr. of chip #1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Low addr. of chip #1

13. 8KB 8KB 8KB 8KB CS CS CS CS Addr[12:0] Addr[13] 2-to-4 decoder Addr[14] IO/M Memory Address Decoding • Implementation of partial decoding • With the above decoding scheme, what happens if the processor accesses location 02117H, 32117H, and 9A117H? • If two 16KB memory chips are used to implement the 32KB memory system, what is the partial decoding circuit? • What are the advantage and disadvantage of partial decoding circuits?

14. D D Q Q Generating Wait States • Wait states are inserted into memory read or write cycles if slow memories are used in computer systems • Ready signal is used to indicate if wait states are needed data Address memory 8088 Delay circuit decoder Ready clr Ready clr clk

15. SRAM v.s. DRAM Static Random Access Memory (SRAM) Dynamic Random Access Memory (DRAM) Storage element • Fast • No refreshing operations • High density and less expensive Advantages • Large silicon area • expensive • Slow • Require refreshing operations Disadvantages High speed memory applications, Such as cache Applications Main memories in computer systems

16. Accessing DRAMs • DRAM block diagram CAS Addr[7:0] Column decoder Storage Array RAS Row decoder RAS CAS Column addr. Row addr. Addr[7:0]

17. Accessing DRAMs • Address bus selection circuit Row Address MUX To DRAM Column Address RAS CAS decoder address D Q D Q D Q Q set set set CLK IO/M

18. Accessing DRAMs • Refreshing operations • Because leakage current will destroy information stored on DRAM capacitors periodic refreshing operations are required for DRAM circuits • During refreshing operation, DRAM circuit are not able to response processor’s request to perform read or write operations • How to suspend memory operations? • DRAM controllers are developed to take care DRAM refreshing operations