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TOPSAccurate is a powerful tool that provides accurate circuit simulations with behavioral simulator speeds for complex PLL designs. It offers time savings, improved accuracy, and comprehensive analysis for meeting tight standards and achieving optimal performance.
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TOPSAccurate TOp Level PLL Simulator April 13, 2007 ©2005-2009 GHz Circuits, Inc.
Background & Motivation Traditional Solutions Proposed Solution TOPS Overview User Interface Example Summary Benefits Extensions Market Segments Contact info Contents ©2005-2009 GHz Circuits, Inc.
PLLs are complicated 3rd or higher order, non-linear, discrete-time, time-varying1 feedback control systems Meeting tight standards mandated goals and even tighter jitter specifications requires extensive expertise, time & compute resources Need answers early in design process for tradeoffs and need exhaustive simulations later on for tolerance/margin/yield analysis There is necessity for a tool which provides circuit-simulator accurate measurements with behavioral-simulator speeds. PLL loop parameters will change with time domain variations in supply (noise) for example, hence these parameters can be considered time-dependent. Also, in some applications like Fractional N synthesizers, the divider counts could be varied in time making the PLL loop parameters time-dependent. Background ©2005-2009 GHz Circuits, Inc.
Standards Mandates • PCI Express • 2MHz < 3dB_BW < 22MHz • 0.54 < z • Peak Jitter Transfer < 3dB • Sonet (OC xxx) • fc < Jitter Transfer Rolloff • Peak Jitter Transfer < 0.1 dB • DVI/HDMI • Jitter transfer amplitude shall not deviate from ideal (single pole 4MHz roll off) by ± 0.2dB from DC to 10MHz • Communications: Jitter performance • Advances in signaling speeds continuously tightens jitter specifications (TX) and losens jitter tolerances (RX) ©2005-2009 GHz Circuits, Inc.
Rely on “Classical” theory/formulae which erroneously force fits the design to possibly 2nd order or continuous time domain Rely on in-house developed behavioral code (such as Matlab etc) Run very time consuming transient simulations After running out of time, Rely on “thumb-rules” and “gut-calls” In summary, either “shoot in the dark and hope to hit the target” or expend incredible amounts time and compute resources Design to Standards Compliance Traditional Methods ©2005-2009 GHz Circuits, Inc.
TOPS: circuit-simulator accurate behavioral simulator with 3-4 orders of magnitude improvement in speed. Use TOPS in the architecture phase to determine PLL parameters to meet specifications Implement circuits per design parameters Use Circuit Simulator to verify functionality and a few step/impulse response closed loop simulations just to verify TOPS accuracy Use TOPS with extracted non-linear sub-circuit characteristics for exhaustive tolerance/margin/yield analysis Use TOPS with time-varying models and noise-scenarios for exhaustive jitter analysis Get the confidence that circuit will meet specifications pre-tapeout and simultaneously reap the benefits of time-savings to tapeout. Solution ©2005-2009 GHz Circuits, Inc.
A Top Level PLL simulator ACCURACY: Within a few % accuracy of circuit simulator, with 3-4 orders of magnitude speed improvement MODELING: Ability model sub-blocks as linear, non-linear or time-varying circuit extracts PARAMETER EXTRACTION: Push button extraction of critical closed loop parameters (ω3dB, Jitter Peak, ζ, ωn, Phase-margin) JITTER ANALYSIS: Comprehensive jitter analysis based on user defined noise vectors TOp level PLL Simulator Overview ©2005-2009 GHz Circuits, Inc.
TOPS: User Interface (i) ©2005-2009 GHz Circuits, Inc.
TOPS: User Interface (ii) ©2005-2009 GHz Circuits, Inc.
Impulse response for a fully differential 6.4GHz LC oscillator is simulated in Circuit Simulator (Cadence Spectre) & TOPS PLL is allowed to lock in Circuit simulator and a Reference Clock phase step of 200ps is applied at 2uS PLL is modeled as a linear system in TOPS with circuit extracted parameters. Next page shows superposition of the phase tracking error & instantaneous VCO frequency for both Circuit Simulator & TOPS Output is viewed with Synopsys AWAVES waveform viewer Case Study: Impulse ResponseComparison with Cadence Spectre ©2005-2009 GHz Circuits, Inc.
Case Study: Impulse ResponseSimulation Results Overlay Spectre TOPS Spectre TOPS ©2005-2009 GHz Circuits, Inc.
Case Study: Impulse ResponseSummary of Results • ACCURACY: The superimposed plots show TOPS step response very closely matches Circuit Simulator phase step response, even using linearized models for TOPS simulation. • Difference in integrated error is within a few % and difference in instantaneous VCO frequency is negligible • Circuit Simulator shows numerical noise in instantaneous frequency plot which is dependent on timestep resolution. • Circuit Simulator run time ~ 10 h • TOPS run time ~ 1.2 s ©2005-2009 GHz Circuits, Inc.
Accurate to Circuit Simulator within a few % Speed improvement of 3-4 orders of magnitude Intuitive & User friendly GUI Push-button extraction of critical design-to parameters Summary ©2005-2009 GHz Circuits, Inc.
Accuracy and significant simulation time savings enable Exhaustive what-if analysis & optimization at architecture level Exhaustive tolerance/margin/yield analysis at post circuit design/layout level Exhaustive Jitter analysis for user specified noise scenarios Formal analog-verification Ability to run bench test measurements prior to tapeout Benefits ©2005-2009 GHz Circuits, Inc.
Reduction in simulation/verification time and time to tape-out Reduction in simulator licenses Reduction in Hardware to run simulators Reduction in Silicon spins Cost Benefits ©2005-2009 GHz Circuits, Inc.
The engine can be extended to benefit other continuous-time systems with discrete-time control SERDES (CDR) RF (Fractional-N synthesizer) Extensions to differentMarket Segments ©2005-2009 GHz Circuits, Inc.
Analog/Mixed-Signal/SOC Chip Design Companies IP design Companies IP purchaser Companies System Companies Verticals ©2005-2009 GHz Circuits, Inc.
Agilent Eagleware Genesys Agilent purchased Eagleware for a few million This however is does not have circuit-accurate modeling of sub-blocks We believe TOPS is significantly faster This does not have post processing engines for optimization/formal-verification etc. Freeware There are a few freely available software but quality, support, verification w.r.t. industrial designs/silicon is unproven WaveCrest This is not exactly competition as Wavecrest has tools to measure similar results post-silicon. One of our goals is to provide WaveCrest type measurements pre-silicon Known Competition ©2005-2009 GHz Circuits, Inc.
Nandu Bhagwan GHz Circuits, Inc 1030 E. El Camino Real, PMB 232 Sunnyvale, CA 94087 1\(408)\7/8/1\0/9/8/9/ www.ghzcircuits.com Nandu_at_ghzcircuits_dot_com Contact Info ©2005-2009 GHz Circuits, Inc.
