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Lecture 25: TPU Programming

Lecture 25: TPU Programming. Computer Engineering 211 Spring 2002. 0x30 4012: Channel Function Select Register 3 (CFSR3). 0x30 400c: Channel Function Select Register 0 (CFSR0). 0x30 400e: Channel Function Select Register 1 (CFSR1). 0x30 4010: Channel Function Select Register 2 (CFSR2).

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Lecture 25: TPU Programming

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  1. Lecture 25: TPU Programming Computer Engineering 211 Spring 2002

  2. 0x30 4012: Channel Function Select Register 3 (CFSR3) 0x30 400c: Channel Function Select Register 0 (CFSR0) 0x30 400e: Channel Function Select Register 1 (CFSR1) 0x30 4010: Channel Function Select Register 2 (CFSR2) Ch 15 Ch 11 Ch 3 Ch 7 Ch 6 Ch 10 Ch 14 Ch 2 Ch 1 Ch 13 Ch 9 Ch 5 Ch 8 Ch 0 Ch 12 Ch 4 Channel Initialization Choose channel function: (input capture): 0xA

  3. 0x30 401c: Channel Priority Register 0 (CPR0) 0x30 401e: Channel Priority Register 1 (CPR1) Ch 15 Ch 3 Ch 11 Ch 7 Ch 10 Ch 6 Ch 2 Ch 14 Ch 9 Ch 13 Ch 1 Ch 5 Ch 4 Ch 0 Ch 12 Ch 8 Channel Initialization Choose channel priority: 0:disable; 1:low; 2:medium; 3: high

  4. 0x30 4018: Host Service Request Register 0 (HSRR0) 0x30 401a: Host Service Request Register 1 (HSRR1) Ch 15 Ch 3 Ch 11 Ch 7 Ch 10 Ch 6 Ch 2 Ch 14 Ch 9 Ch 13 Ch 1 Ch 5 Ch 4 Ch 0 Ch 12 Ch 8 Channel Function Activation After initializing channel, the channel function is activated by host service request, which can be further specialized (parameters) through host sequence.

  5. Input Capture Host ServiceRequest 00: No host service (reset) 01: Initialize TCR mode 10: initialize parameter mode 11: not used

  6. 0x30 4014: Host Sequence Register 0 (HSQR0) 0x30 4016: Host Sequence Register 1 (HSQR1) Ch 15 Ch 3 Ch 11 Ch 7 Ch 2 Ch 6 Ch 14 Ch 10 Ch 9 Ch 5 Ch 1 Ch 13 Ch 12 Ch 4 Ch 0 Ch 8 Host Sequence Input Capture Host Sequence 00: single shot, no links 01: continual, no links 10: single shot, links 11: continual, links

  7. Typical Initialization Sequence • Disable the channel before programming it. • CPR[ch]  00 (channel priority – disabled) • Assign the channel function: • CFSR[ch]  0xA (for input capture/ITC) • Program the function parameters: • IC requires: MAX_COUNT, Channel control • MAX_COUNT=1 for input capture • Channel control: TBS: 000x (input channel; capture TCR1); PAC: 001 (detect rising edge); PSC: 11 (do not force) • Write 000000111 (0x7) to 0x30 4100 for Ch 0. • Write 100 to 0x30 4104 for Ch 0.

  8. Initialization Sequence Contd. • Program the function parameters: • Host sequence single shot, no links. Write 00 into HSQRR[ch]. • Initialize host service (activate the channel): • HSRR[ch]  01 (initialize TCR mode) • Enable the channel: • CPR[ch]  01, 10, 11

  9. Channel Initialization lis r5, 0x30 //base addr of TPU memory space // disable channel 0 lhz r6, 0x401e(r5) // load CPR1 andi r6, r6, 0xfffc // 0 into LSB 2 bits sh r6, 0x401e(r5) // channel function select, 0xa for IC/ITC lhz r6, 0x4012(r5) // load CFSR3 andi r6, r6, 0xfff0 // 0 into LSB 2 bits ori r6, r6, 0xa //0xa in LSB 2 bits sh r6, 0x401e(r5) // channel control li r6, 0x7 sh r6, 0x4100(r5)

  10. Channel Initialization contd. //MAX_COUNT li r6, 100 sh r6, 0x4104(r5) // Host sequence lhz r6, 0x4016(r5) andi r6, r6, 0xfffc sh r6, 0x4016(r5) // host service request li r6, 0x1 sh r6, 0x401a(r5) // enable the channel : priority 11 lhz r6, 0x401e(r5) // load CPR1 ori r6, r6, 0x3 // 11 into LSB 2 bits sh r6, 0x401e(r5)

  11. 0x30 401a: Host Service Request Register 1 (HSRR1) Ch 7 Ch 3 Ch 6 Ch 2 Ch 5 Ch 1 Ch 4 Ch 0 Shared Register Modification 00: host service complete  by TPU channel 01: Initialize TCR mode  by CPU Program Modification of HSRR involves read-modify-write: lhz r6, 0x401a(r5) //read andi r6, r6, 0xfffc // modify (write %01 to HSRR[ch0]) ori r6, r6, 0x1 sh r6, 0x401a(r5) // write Does it work? How many independent potential writers into HSRR1?

  12. 00 00 00 00 00 00 00 11 00 00 11 11 10 01 00 10 10 01 01 00 00 00 00 00 lhz r6, 0x401a(r5) //read andi r6, r6, 0xfffc // modify (write %01 to HSRR[ch0]) Ori r6, r6, 0x1 sh r6, 0x401a(r5) // write Shared Register Modification Contd. We don’t really know what happens to ch 1-7 fields while we modify ch 0 field.

  13. 00 00 Ch 3 Ch 7 Ch 2 00 11 Ch 6 Ch 5 10 00 Ch 1 Ch 0 00 00 Ch 4 01 Write guard logic only allows 01, 10, 11 to go through! Shared Register Modification Contd. Solution: into ch 1-7 fields write something we are definitely not supposed to write. 00 is written by only the TPU, no CPU program should legitimately write that value. li r6, 0x1 //00 00 00 00 00 00 01 sh r6, 0x401a(r5)

  14. Interrupt Service Procedure for IC/ITC Ch0-ISR: //load TPU base addr in r5 lis r5, 0x30 //disable ch 0 interrupt lhz r6, 0x400a(r5) andi r6, r6, 0xfffe //CIER[ch0]  0 sh r6, 0x400a(r5) // clear the ch0 interrupt status field li r6, 0xfffe // 1111 1111 1111 1110 sh r6, 0x4020(r5) //CISR[ch0]  0 // read FINAL_TRANS_TIME into addr in r7 lhz r6, 0x4108(r5) sh r6, 0(r7) // return blr/rfi

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