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Fiber Channel Video Controller uArchitecture Review. Tsachy Kapchitz & Michael Grinkrug Super.: Alex Gurevich Technion Digital Lab, Elbit Systems. Project Goals. Design a controller that receives FC traffic from an external receiver and passes to memory only video data directed to it.
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Fiber Channel Video ControlleruArchitecture Review Tsachy Kapchitz & Michael Grinkrug Super.: Alex Gurevich Technion Digital Lab, Elbit Systems
Project Goals • Design a controller that receives FC traffic from an external receiver and passes to memory only video data directed to it. • The controller should be with minimal latency.
Block Diagram • Input: • HP Receiver • Output: • SRAM • Interface: • Config. Params (address, video params etc.) • Status Register
Functionality: Get data [words], comma and clock from HP receiver Combine the data into DW and pass to Frame Controller Generate clock of half the frequency of the clock provided by HP receiver Pass COM_DET signal with the relevant DW Input: (from HP receiver) Data [15:0] COM_DET signal Clock (RBC) Output: (to Frame Controller) Data [31:0] Comma signal Clock (half the frequency of RBC) Input Unit
Input Unit - clock generation • This clock (f/2) will be the operating clock of the controller (Frame / container controllers) • Memory Unit (address placement and SRAM interface) will work @ 2f
Input Unit - Assumptions • HP Receiver operates in 2-Bytes per clock mode (not Ping-Pong) • FC frames are DW aligned, so comma always will be passed in parallel with SOF / EOF • The data from HP is in 8 bits per Byte format (after 10 to 8 conversion)
Functionality: Receive data from Input Unit by DW Analyze the data on FC Header level Pass the relevant payload to Container Controller Generate FC frame status Input: (from Input Unit) Data [31:0] Clock (half of RBC) Comma signal Output: (to Container Controller) Data [31:0] Valid + BC New_Container Frame Status Register Frame Controller
Frame Controller - Block Diagram • Frame header Analyzer - main FSM, that parses FC frame header fields • Sequence Follower - figures the next expected sequence num. and sequence count • CRC is only compared and OK/NOK bit set in status register • Suspender - FIFO of depth 2 that suspends the data in order to get the end of the frame (CRC)
Frame Controller - uArchSequence Follower • New_container is a pulse that accompanies the first DW of container header
Frame Controller - uArchSuspender • BC : • 11 - DW • 10 - 3 Bytes • 01 - 2 Bytes • 00 - 1 Byte • @comma - #byte_fill
Frame Controller - Assumptions • Sequence on FC level 1 video container • Single sequence at a time (one video stream) • The link is FIFO (no surpassing frames) • Point to point connection (single sender) • If an error on FC frame level occurs - current sequence will be discarded (thus current video frame will be partially lost) • Upon CRC error only, the data will be passed through and an appropriate status will be generated
Functionality: Get container from Frame Controller and write video objects to memory using an appropriate method, according to video system (with help of Memory Unit) Write ancillary object to a separate memory Input: (from Frame Controller) Data [31:0] BC Valid New_Container Memory Unit interface Output: (to Memory Unit) SRAM interface Memory Unit interface Container Controller
Obj. Extractor Data Object Info SIZE Frame Contrl. Container Controller -Header Analyzer (cont.) • Data flows through the block and relevant fields are checked and loaded into Object Information registers • Objects size is loaded into a “temp” register and transferred together with offset
Container Controller - Assumptions • Memory Unit gets Index of the first valid (TYPE & Size) object • @ interlaced mode - video field object • Single video stream