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This course introduces modeling languages and tools, design space estimation, and team project tasks in HW/SW codesign. Students learn to overcome complexity through practical works designing games. The agenda covers English teachings, affordable development boards, HDLs, VLSI synthesis, digital system, and projects in ascending complexity levels. Laboratory tasks focus on HW design, graphical applications, Xilinx PicoBlaze, and various HW/SW ratios. Obtained results and future enhancements aim to address issues, upgrade soft-core processors, and extend FPGA board compatibility.
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EWME 2010-05-11 Learning-by-gaming in HW/SW codesign Vadim Pesonen, Maksim Gorev, Kalle Tammemäe
Introduction and course objectives Planning the course and practical works Laboratory work assignments Obtained results Future enhancements EWME 2010-05-11 Learning-by-gaming in HW/SW codesign
Modelling languages and tools Design space Estimate and analyze to partition Predefined IP cores Accomplish team tasks EWME 2010-05-11 Introduction and course objectives • Laboratory works for HW/SW codesign course • Overcome complexity with entertaining practical works • Learn by designing games Students must be aware of/be able to:
Introduction and course objectives Planning the course and practical works Laboratory work assignments Obtained results Future enhancements EWME 2010-05-11 Agenda
English as the primary language Materials available online Affordable development boards Consider students’ background knowledge Introduction to HDLs VLSI synthesis Digital system design System-on-a-chip design Numerous projects EWME 2010-05-11 Planning the course and practical works
Introduction and course objectives Planning the course and practical works Laboratory work assignments Obtained results Future enhancements EWME 2010-05-11 Agenda
4 levels in ascending complexity order Introductory Beginner – simple HW design in VHDL/Verilog Intermediate – graphical application Advanced – complex design Various HW/SW ratios EWME 2010-05-11 Laboratory work assignments
4 levels in ascending complexity order Introductory Beginner – simple HW design in VHDL/Verilog Intermediate – graphical application Advanced – complex design Several HW/SW partitions EWME 2010-05-11 Laboratory work assignments
4 levels in ascending complexity order Introductory Beginner – simple HW design in VHDL/Verilog Intermediate – graphical application Advanced – complex design Various HW/SW ratios EWME 2010-05-11 Laboratory work assignments
4 levels in ascending complexity order Introductory Beginner – simple HW design in VHDL/Verilog Intermediate – graphical application Xilinx PicoBlaze soft-core processor Advanced – complex design Various HW/SW ratios EWME 2010-05-11 Laboratory work assignments
4 levels in ascending complexity order Introductory Beginner – simple HW design in VHDL/Verilog Intermediate – graphical application Advanced – complex design Various HW/SW ratios EWME 2010-05-11 Laboratory work assignments
Introduction and course objectives Planning the course and practical works Laboratory work assignments Obtained results Future enhancements EWME 2010-05-11 Agenda
+ Good course objective coverage + Generally positive students’ reaction + Strong team spirit during practical works – Insufficient practical work guides – Complexity gap between assignments - 1/3 failed the laboratory tasks – Used soft-core processor insufficient EWME 2010-05-11 Obtained results
Introduction and course objectives Planning the course and practical works Laboratory work assignments Obtained results Future enhancements EWME 2010-05-11 Agenda
Address negative feedback Employ more powerful soft-core processors Xilinx MicroBlaze OpenRISC Coffee RISC core Extend board usage Different FPGA platforms EWME 2010-05-11 Future enhancements
