xc2200

1. xc2200 Infenion microcontroller PRESENTED BY SADAF ABBASI

2. FEATURES • ALU(16 BIT) • MAC • ADU • PMU • DMU • PSRAM(32K byte) • DSRAM(16K byte) • DPRAM(2Kbyte) • SBRAM(8Kbyte) • ADDRESS BUS(0-24bits) • DATA BUS(8/16 bits) • BUS OPERATION (multiplexed or de multiplexed) • 80 Mhz

3. FEATURES (continued) • Instruction Fetch Unit (IFU), • Register File (RF), • Dedicated Special Function Registers (SFRs).

4. INSTRUCTIONS • The instruction cycle time is dramatically reduced through the use of instruction pipelining. • This technique allows the core CPU to process portions of multiple sequential • Instruction stages in parallel. • Based on the hardware provisions, most of the XC2200M’s instructions can be executed in just one clock cycle (1/fSYS).

5. Instructions includes: • Arithmetic instructions, logic instructions, • and move instructions with most addressing modes. • Special instructions such as JMPS take more than one machine cycle. • Divide instructions are mainly executed in the background, so other instructions can be executed in parallel.

6. COMPONENTS DISCRIPTION • Unit (ALU) performs all standard (word) arithmetic and logical operations. • The Multiply and Accumulate Unit (MAC) performs extended arithmetic operations such as 32-bit addition, 32-bit subtraction, and single-cycle 16-bit × 16-bit multiplication. • The Address Data Unit (ADU) contains two independent arithmetic units to generate, calculate, and update addresses for data accesses.

7. DESCRIPTION (CONTD) • The Program Management Unit (PMU) controls accesses to the on-chip program memory blocks such as the ROM/Flash module and the Program/Data RAM (PSRAM) and also fetches instructions from external memory. • The Data Management Unit (DMU) controls accesses to the on-chip Data RAM (DSRAM), to the on-chip peripherals connected to the peripheral bus, and to resources on the external bus. External accesses (including accesses to peripherals connected to the on-chip LXBus) are executed by the External Bus Controller (EBC). • The 16-bit interface between the DMU and the CPU handles all data transfers (operands). • Data accesses by the CPU are distributed to the appropriate buses according to the defined address map. • 16 GPRS

8. DESCRIPTION • -chip Flash memory store code or constant data. • 16 Kbytes of on-chip Data SRAM (DSRAM) are provided as a storage for general user data. • 2 Kbytes of on-chip Dual-Port RAM (DPRAM) are provided as a storage for user • defined variables, for the system stack, and in particular for general purpose register banks. System relevant • user data that must be preserved while the major part of the device is powered • down. • 8 Kbytes of on-chip Stand-By SRAM (SBRAM) are provided as a storage for

9. BLOCK DIAGRAM

11. PINS DESCRIPTION

12. MODES

13. PERIPHERALS

15. Two synchronizable A/D converters with 24 channels, optional data preprocessing, and a conversion time down to 1.2 µs • 16-Channel general purpose capture/compare unit • Multiple capture/compare units for flexible PWM signal generation (3 capture/compare channels and 1 compare channel) • Multi-functional general purpose timer unit with 5 timers • Multiple serial interface channels to be used as UART, LIN, SPI/QSPI, IIC Bus

16. Programmable watchdog timer and oscillator watchdog • Enhanced power saving modes with flexible power management • On-chip real time clock • On-chip bootstrap loader • On-chip debug support via JTAG interface • Interface, IIS Interface (optional) active • Temperature range: -40° to +125°C • Single Power Supply from 3.0 V to 5.5 V

17. PARALLEL PORTS

18. COMPARISON • 8051 68HC11 XC2200 • 8bit cpu 8Bit cpu 32 bits • 4kb Ram 256B Ram 16kb • 12Mhz clock 2 Mhz 80Mhz 4 PORTS 16 PORTS • Extra flash memory

19. THANKS