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Lecture 17: Basic Pipelining

Lecture 17: Basic Pipelining. Today’s topics: 5-stage pipeline Hazards and instruction scheduling Mid-term exam stats: Highest: 90, Mean: 58. Multi-Cycle Processor. Single memory unit shared by instructions and memory Single ALU also used for PC updates

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Lecture 17: Basic Pipelining

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  1. Lecture 17: Basic Pipelining • Today’s topics: • 5-stage pipeline • Hazards and instruction scheduling • Mid-term exam stats: • Highest: 90, Mean: 58

  2. Multi-Cycle Processor • Single memory unit shared by instructions and memory • Single ALU also used for PC updates • Registers (latches) to store the result of every block

  3. The Assembly Line Unpipelined Start and finish a job before moving to the next Jobs Time A B C Break the job into smaller stages A B C A B C A B C Pipelined

  4. Performance Improvements? • Does it take longer to finish each individual job? • Does it take shorter to finish a series of jobs? • What assumptions were made while answering these • questions? • Is a 10-stage pipeline better than a 5-stage pipeline?

  5. Quantitative Effects • As a result of pipelining: • Time in ns per instruction goes up • Each instruction takes more cycles to execute • But… average CPI remains roughly the same • Clock speed goes up • Total execution time goes down, resulting in lower average time per instruction • Under ideal conditions, speedup = ratio of elapsed times between successive instruction completions = number of pipeline stages = increase in clock speed

  6. A 5-Stage Pipeline

  7. A 5-Stage Pipeline Use the PC to access the I-cache and increment PC by 4

  8. A 5-Stage Pipeline Read registers, compare registers, compute branch target; for now, assume branches take 2 cyc (there is enough work that branches can easily take more)

  9. A 5-Stage Pipeline ALU computation, effective address computation for load/store

  10. A 5-Stage Pipeline Memory access to/from data cache, stores finish in 4 cycles

  11. A 5-Stage Pipeline Write result of ALU computation or load into register file

  12. Conflicts/Problems • I-cache and D-cache are accessed in the same cycle – it • helps to implement them separately • Registers are read and written in the same cycle – easy to • deal with if register read/write time equals cycle time/2 • (else, use bypassing) • Branch target changes only at the end of the second stage • -- what do you do in the meantime? • Data between stages get latched into registers (overhead • that increases latency per instruction)

  13. Hazards • Structural hazards: different instructions in different stages • (or the same stage) conflicting for the same resource • Data hazards: an instruction cannot continue because it • needs a value that has not yet been generated by an • earlier instruction • Control hazard: fetch cannot continue because it does • not know the outcome of an earlier branch – special case • of a data hazard – separate category because they are • treated in different ways

  14. Structural Hazards • Example: a unified instruction and data cache  • stage 4 (MEM) and stage 1 (IF) can never coincide • The later instruction and all its successors are delayed • until a cycle is found when the resource is free  these • are pipeline bubbles • Structural hazards are easy to eliminate – increase the • number of resources (for example, implement a separate • instruction and data cache)

  15. Data Hazards

  16. Bypassing • Some data hazard stalls can be eliminated: bypassing

  17. Data Hazard Stalls

  18. Data Hazard Stalls

  19. Example add $1, $2, $3 lw $4, 8($1)

  20. Example lw $1, 8($2) lw $4, 8($1)

  21. Example lw $1, 8($2) sw $1, 8($3)

  22. Control Hazards • Simple techniques to handle control hazard stalls: • for every branch, introduce a stall cycle (note: every 6th instruction is a branch!) • assume the branch is not taken and start fetching the next instruction – if the branch is taken, need hardware to cancel the effect of the wrong-path instruction • fetch the next instruction (branch delay slot) and execute it anyway – if the instruction turns out to be on the correct path, useful work was done – if the instruction turns out to be on the wrong path, hopefully program state is not lost

  23. Branch Delay Slots

  24. Slowdowns from Stalls • Perfect pipelining with no hazards  an instruction • completes every cycle (total cycles ~ num instructions) •  speedup = increase in clock speed = num pipeline stages • With hazards and stalls, some cycles (= stall time) go by • during which no instruction completes, and then the stalled • instruction completes • Total cycles = number of instructions + stall cycles

  25. Title • Bullet

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