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Texas Instruments Incorporated European Customer Training Centre University of Applied Sciences Zwickau (FH)

Module 13 : C28x BOOT – ROM. 32-Bit-Digital Signal Controller TMS320F2812. Texas Instruments Incorporated European Customer Training Centre University of Applied Sciences Zwickau (FH). TMS320F2812 Memory Map. MO SARAM (1K). M1 SARAM (1K). reserved. PF 0 (2K). reserved. PIE vector

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Texas Instruments Incorporated European Customer Training Centre University of Applied Sciences Zwickau (FH)

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  1. Module 13 : C28x BOOT – ROM 32-Bit-Digital Signal Controller TMS320F2812 Texas Instruments Incorporated European Customer Training Centre University of Applied Sciences Zwickau (FH)

  2. TMS320F2812 Memory Map MO SARAM (1K) M1 SARAM (1K) reserved PF 0 (2K) reserved PIE vector (256) ENPIE=1 reserved XINT Zone 0 (8K) reserved XINT Zone 1 (8K) reserved PF 2 (4K) reserved PF 1 (4K) LO SARAM (4K) L1 SARAM (4K) XINT Zone 2 (0.5M) reserved XINT Zone 6 (0.5M) OTP (1K) reserved FLASH (128K) HO SARAM (8K) XINT Zone 7 (16K) MP/MC=1 Boot ROM (4K) MP/MC=0 XINT Vector-RAM (32) MP/MC=1 ENPIE=0 Data | Program Data | Program 0x00 0000 0x00 0400 0x00 0800 0x00 0D00 0x00 2000 0x00 1000 0x00 4000 0x00 6000 0x00 7000 0x00 8000 reserved 0x00 9000 0x08 0000 0x00 A000 0x10 0000 0x3D 7800 0x18 0000 0x3D 7C00 0x3D 8000 reserved 128-Bit Password 0x3F 8000 0x3F A000 reserved 0x3F C000 0x3F F000 0x3F FFC0 BROM vector (32) MP/MC=0 ENPIE=0

  3. Reset – Boot Loader XMPNMC=1 (microprocessor mode) Reset OBJMODE=0 AMODE=0 ENPIE=0 VMAP=1 M0M1MAP=1 XMPNMC=0 (microcomputer mode) Reset vector fetched from boot ROM 0x3F FFC0 Reset vector fetched from XINTF zone 7 0x3F FFC0 Execution Bootloading Entry Point Routines FLASH SPI H0 SARAM SCI-A OTP Parallel load Boot determined by state of GPIO pins Notes: F2810 XMPNMC tied low internal to device XMPNMC refers to input signal MP/MC is status bit in XINTFCNF2 register XMPNMC only sampled at reset

  4. Boot Loader Options GPIO pins F4 F12 F3 F2 1 x x x jump to FLASH address 0x3F 7FF6 * 0 0 1 0 jump to H0 SARAM address 0x3F 8000 * 0 0 0 1 jump to OTP address 0x3D 7800 * 0 1 x x bootload external EEPROM to on-chip memory via SPI port 0 0 1 1 bootload code to on-chip memory via SCI-A port 0 0 0 0 bootload code to on-chip memory via GPIO port B (parallel) * Boot ROM software configures the device for C28x mode before jump

  5. Reset Code Flow - Summary 0x3D 7800 OTP (2K) 0x3D 8000 FLASH (128K) 0x3F 7FF6 0x3F 8000 H0 SARAM (8K) Execution Entry Point Determined By GPIO Pins 0x3F F000 Boot ROM (4K) Boot Code 0x3F FC00     BROM vector (32) 0x3F FFC0 0x3F FC00 RESET Bootloading Routines (SPI, SCI-A, Parallel Load)

  6. TMS320F2812 BOOT-ROM Memory Map Int. Vectors; 62 x 16 0x3F FFC0 – 0x3F FFC1 0x3F F000 – 0x3F F501 0x3F F502 – 0x3F F711 0x3F F712 – 0x3F F833 0x3F F834 – 0x3F F9E7 0x3F FFC2 – 0x3F FFFF 0x3F FB50 – 0x3F FBFF SIN/COS; 641 x 32(Q30) Normal. Inverse; 264 x 32(Q29) Normal. Sqrt;145 x32(Q30) Normal. Arctan; 218 x32(Q30) Round/Sat. 180 x 32(Q30) reserved Bootloader ; 960 x 16 RESET – Vector; 2 x 16 Address Range Data & Program Space 0x3F F9E8 – 0x3F FB4F 0x3F FC00 – 0x3F FFBF

  7. C28x BOOT-ROM Vector Table RESET INT1 INT2 INT3 INT4 INT5 INT6 INT7 INT8 0x3FFFCA INT9 INT11 INT12 INT13 INT14 DLOGINT 0x3F FFC0 0x3F FFC2 0x3F FFC4 0x3FFFC6 INT10 0x3FFFCC 0x3FFFC8 0x3FFFD0 0x00007E 0x3FFFD2 0x3FFFD4 0x3FFFD6 0x3FFFD8 0x3FFFDA 0x3FFFDC 0x3FFFDE 0x3FFC00 0x000042 0x000046 0x00 0044 0x3FFFCE 0x000048 0x00004A 0x00004C 0x00004E 0x000050 0x000052 0x000054 0x000056 0x000058 0x00005E 0x00005A 0x3FFFEE RTOSINT reserved NMI ILLEGAL USER 1 USER 2 USER 3 USER 4 USER 5 USER 6 USER 7 USER 8 USER 9 USER 10 USER 11 USER 12 0x3F FFE0 0x3F FFE2 0x3F FFE4 0x3FFFE6 0x3FFFE8 0x00005C 0x00007C 0x3FFFEA 0x3FFFF0 0x3FFFF2 0x3FFFF4 0x3FFFF6 0x3FFFF8 0x3FFFFA 0x3FFFFC 0x3FFFFE 0x3FFFEC 0x000062 0x00 0064 0x00 0060 0x000068 0x00007A 0x000066 0x000076 0x000074 0x000078 0x000070 0x00006E 0x00006C 0x00006A 0x000072 Vector Address Content Address Content Vector

  8. Boot Loader Data Stream Structure 1 N 12 0x10AA : Key for memory width = 16 bit Last word of block Block Size (words); if 0 then end of transmission 2-9 N+1 13 Destination Address of block ; Addr[31:16] Reserved for future use Block Size (words) 14 10 N+2 Destination Address of block ; Addr[15:0] Entry Point PC[22:16] Destination Address of block ; Addr[31:16] N+3 15 11 Entry Point PC[15:0] First word of block Destination Address of block ; Addr[15:0]

  9. Boot Loader Data Stream Example 10AA ; Key for 16-Bit memory stream 0000 0000 0000 0000 0000 0000 0000 0000 003F ; PC – starting point after load is complete: 0x3F 8000 8000 0005 ; 5 words in block 1 003F 9010 ; First block is loaded into 0x3F 9010 0001 ; first data word 0002 0003 0004 0005 ; last data 0002 ; Second block is two words long 003F ; Second block is loaded into 0x3F 8000 8000 7700 ; first data 7625 ; last data 0000 ; next block zero length = end of transmission

  10. C28x Boot Loader Transfer Procedure Read first word(W1) W1= 0x10AA? Read second word lower 8 bit No Yes W2:W1= 0x08AA? Format Error 16bit data size No Read Entry Point Yes Read BlockSize(R) 8bit data size R = 0? Yes No Read BlockAddress Return and Jump to Entry Point Transfer R words from source to destination

  11. C28x Init Boot Function RESET Init Boot Initialize C28x: OBJMODE = 1 AMODE = 0 M0M1MAP = 1 DP = 0 OVM = 0 SPM = 0 SP = 0x00 0400 Call BootModeSelect Dummy Read CSM passwords ExitBoot

  12. C28x SCI Boot Loader Function RS 232 e.g. Texas MAX232 TxD 2 C28x SCI-A Host/ e.g. PC‘s COM1 RS 232 TxD RxD RxD 3

  13. C28x SCI Boot Function SCI Boot Enable SCI-A Clock Set LSPCLK to /4 Echo auto baud character Enable SCI-A Tx and Rx - Pin Read KeyValue Setup SCI-A: 1 stop,8 data ,no parity No loopback Disable SCI-A INT Disable SCI-A FIFO Valid Key? No FLASH Yes Prime SCI-A baud rate register Start Boot Load Sequence Enable Autobaud detection Autobaud Lock ? Yes No

  14. C28x parallel Boot Loader (GPIO) GPIO-D6 C28x GPIO Host/ e.g. PC‘s COM1 GPIO-D5 16 GPIO-B0..B15 1: C28 indicates: “ready to receive” 2: Host signals “data active at GPIO-B” 3: C28 indicates “read is complete” 4: Host acknowledges “cycle completed” 5: C28x indicates: “ready for more data” GPIO-D6 GPIO-D5 1 2 3 4 5 6

  15. C28x GPIO Boot Function GPIO Boot Read and discard 8 reserved words Initialize GPIO GPIO-B = input GPIO-D5 = input GPOI-D6 = output Read Entry Point Read KeyValue ( 8 or 16 Bit size) Call Parallel Copy Data Valid Key? Yes Jump Entry Point No FLASH

  16. Host GPIO Boot Function Start Download C28x ack? (GPIO-D6=1) No C28x ready? (GPIO-D6=0) No Yes Yes Deactivate GPIO-D5 =1 Load data Signal that data avail. GPIO-D5 =0 More Data? Yes No End Download

  17. C28x SPI Boot Loader Function Serial EEPROM DIN DOUT CLK /CS SPI - MOSI C28x SPI SPI - SOMI SPI - CLK GPIO – F3 ST M95080 – see Module 7 • Note: • SPI – loader is 8bit only, it does not support 16bit data stream • EEPROM data stream must start at address 0x0000

  18. C28x SPI Boot Loader Data Stream Byte Content 1 LSB = 0xAA ( Key for 8bit transfer) 2 MSB = 0x08 ( Key for 8bit transfer) 3 LSB = LSPCLK value 4 MSB = SPIBRR value 5-18 reserved 19 Entry Point [23:16] 20 Entry Point [31:24] 21 Entry Point [7:0] 22 Entry Point [15:8] 23 ... Blocks of data: block size/destination/data as shown

  19. C28x SPI Boot Function SPI - Boot Read KeyValue Enable SPI clock Set LSPCLK to 4 Valid Key? ( 0x08AA ) No FLASH Enable SPI pin – functionality Yes Read LSPCLK value Setup SPI: 8-bit character Internal SPI-clock SPI-Master Slowest baud rate (0x7F) Relinquish from RESET Requested LSPCLK = 2? No Set chip enable GPIO-F3 = 1 Yes Change LSPCLK Send Read Command To EEPROM Address = 0x0000 C

  20. C28x SPI Boot Function (cont.) C Read SPIBRR value Requested SPIBRR = 0x7F? No Change SPIBRR Yes Read 7 reserved words Read Data Blocks Jump EntryPoint Read Entry Point

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