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EE435 Final Project: 9-Bit SAR ADC

EE435 Final Project: 9-Bit SAR ADC. Curtis Mayberry, Kyle Slinger, Yuan Ji( 计元 ). 9-Bit SAR ADC. Requirements 9 bits of resolution INL ± 1 LSB DNL ± 1 LSB Speed > 0.2 MSPS Power < 20 mW Area < 1 mm^2. System Design. SAR ADC system level design. System Level Design.

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EE435 Final Project: 9-Bit SAR ADC

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  1. EE435 Final Project: 9-Bit SAR ADC Curtis Mayberry, Kyle Slinger, Yuan Ji(计元)

  2. 9-Bit SAR ADC Requirements • 9 bits of resolution • INL ± 1 LSB • DNL ± 1 LSB • Speed > 0.2 MSPS • Power < 20 mW • Area < 1 mm^2

  3. System Design SAR ADC system level design

  4. System Level Design

  5. Charge Redistribution DAC Design • Charge Redistribution (Q=CV and Q is conserved) • 2 cycles sampling • Estimate bit by bit

  6. 9-bit SAR ADC Final Schematic

  7. 9-bit SAR ADC Switch Device Sizing Transmission Gate Style Switch Used for Vin Tracking Single Transistor Switches Used for Vdd and Vss Smallest switch nmos=1.5um wide by 600nm long Smallest switch pmos=4.5um wide by 600nm long Sizes increase proportionally to capacitor sizes 4 sizes used. Largest can drive largest capacitor full range in 50ns.

  8. 9-bit SAR ADC Switches

  9. 9-bit SAR ADC Switch Testing Switching with the largest switch and largest load capacitor Approximately 50 ns required for maximum rise and fall time. This corresponds to 20 MSPS

  10. 9-bit SAR ADC Switch Testing

  11. 9-bit SAR ADC Switch Testing

  12. 9-bit SAR ADC Capacitor Array

  13. 9-bit SAR ADC Comparator

  14. 9-bit SAR ADC Comparator Performance • DC Gain: 79.91 dB • Resolution: 0.5 mV • 3 dB Bandwidth: 26.87 MHz • Propagation Delay(1 LSB step): 6.5 ns • Hysteresis Voltage: +- 1.815 mV • Power Consumption: 2 mW

  15. 9-bit SAR ADC Comparator Design Strategy

  16. 9-bit SAR ADC Comparator 1st Stage

  17. 9-bit SAR ADC Comparator 2nd Stage

  18. 9-bit SAR ADC Comparator Hysteresis

  19. 9-bit SAR ADC Comparator 3rd Stage

  20. 9-bit SAR ADC Propagation Delay(1 LSB step)

  21. 9-bit SAR ADC Propagation Delay vs. Overdrive Amplitude

  22. Digital SAR Logic HDL design HDL simulation in Modelsim Elaboration Results Synthesis Results Initial Verification Test Bench Final Implementation

  23. FSM Diagram

  24. HDL simulation Testbench Scenario 1

  25. HDL simulation Testbench Scenario 2

  26. HDL simulation Results

  27. Elaboration

  28. Synthesized Digital Control

  29. Final Digital Schematic

  30. Spectral and Static Performance Spectral analysis, INL, and DNL

  31. INL, DNL, and Spectral Testing Test Bench

  32. Spectrum Analysis of the ADC • Signal Frequency : 312.5 KHz • Sampling Frequency: 946.745 Khz • M=512 • K=169

  33. DNL: First fifth of code • Ran for 100us of a 543us ramp • Decreased run time • 0.99 DNL over this range

  34. INL over 100us from 0 to FS code • 6.4 LSB INL • 11 LSB offset

  35. INL and DNL over 543us, covering FS INL = 15.3 LSB INL index: 4.692 *10^-4 DNL = 1.99 LSB DNL time: 1.122 *10^-4

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