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Pertemuan 9 Mesin ARM: I

Pertemuan 9 Mesin ARM: I. Matakuliah : T0324 / Arsitektur dan Organisasi Komputer Tahun : 2005 Versi : 1. Learning Outcomes. Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : Membandingkan implementasi instruksi mesin untuk Arsitektur Komputer ARM ( C4 ) ( No TIK : 4 ).

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Pertemuan 9 Mesin ARM: I

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  1. Pertemuan 9Mesin ARM: I Matakuliah : T0324 / Arsitektur dan Organisasi Komputer Tahun : 2005 Versi : 1

  2. Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : • Membandingkan implementasi instruksi mesin untuk Arsitektur Komputer ARM ( C4 ) ( No TIK : 4 )

  3. Chapter 3. ARM Instruction Set: I

  4. LDR R1,N Load coun t in to R1. LDR R2,POINTER Load address NUM1 in to R2. MOV R0,#0 Clear accum ulator R0. LOOP LDR R3,[R2],#4 Load next n um b er in to R3. ADD R0,R0,R3 Add n umber in to R0. SUBS R1,R1,#1 Decremen t lo op coun ter R1. BGT LOOP Branc h back if not done. STR R0,SUM Store sum. Figure 3.7. An ARM program for adding numbers.

  5. Memory Addressing address or data lab el Operation information Assembler directives AREA CODE ENTR Y Statements that LDR R1,N generate LDR R2,POINTER mac hine MO V R0,#0 instructions LOOP LDR R3,[R2],#4 ADD R0,R0,R3 SUBS R1,R1,#1 BGT LOOP STR R0,SUM Assembler directives AREA D A T A SUM DCD 0 N DCD 5 POINTER DCD NUM1   NUM1 DCD 3, 17,27, 12,322 END Figure 3.8. ARM assembly language source program for the program in Figure 3.7.

  6. LDR R0,POINTER Load address LOC in to R0. LDRB R1,[R0] Load ASCI I c haracters LDRB R2,[R0,#1] in to R1 and R2. AND R2,R2,#&F Clear high-order 28 bits of R2. ORR R2,R2,R1,LSL #4 Or [R1] shifted left in to [R2]. STRB R2,P A CKED Store pac k ed BCD digits in to P A CKED. Figure 3.5. An ARM program for packing two 4-bit decimal digits into a byte.

  7. Pertemuan 10Mesin ARM: II Matakuliah : T0324 / Arsitektur dan Organisasi Komputer Tahun : 2005 Versi : 1

  8. Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : • Membandingkan implementasi instruksi mesin untuk Arsitektur Komputer ARM ( C4 ) ( No TIK : 4 )

  9. Chapter 3. ARM Instruction Set: II

  10. READ LDR R3,[R1] Load [INST A TUS] and TST R3,#8 w ait for c haracter. BEQ READ LDRB R3,[R1,#4] Read the c haracter and STRB R3,[R0],#1 store it in memory . ECHO LDR R4,[R2] Load [OUTST A TUS] and TST R4,#8 w ait for displa y BEQ ECHO to b e ready . STRB R3,[R2,#4] Send c haracter to displa y . TEQ R3,#CR If not carriage return, BNE READ read more c haracters. Figure 3.9. An ARM program that reads a line of characters and displays it.

  11. Calling program LDR R1,N LDR R2,POINTER BL LIST ADD STR R0,SUM . . . Subroutine LIST ADD STMFD R13!, { R3,R14 } Sa v e R3 and return address in R14 on stac k, using R13 as the stac k p oin ter. MO V R0,#0 LOOP LDR R3,[R2],#4 ADD R0,R0,R3 SUBS R1,R1,#1 BGT LOOP LDMFD R13!, { R3,R15 } Restore R3 and load return address in to PC (R15). Figure 3.10. Program of Figure 3.7 written as an ARM subroutine; parameters passed through registers.

  12. ADR R1,A VEC R1 p oin ts to v ector A. ADR R2,BVEC R2 p oin ts to v ector B. LDR R3,N R3 is the lo op coun ter. MO V R0,#0 R0 accum ulates the dot pro duct. LOOP LDR R4,[R1],#4 Load A comp onent. LDR R5,[R2],#4 Load B comp onent. MLA R0,R4,R5,R0 Multiply comp onen ts and accum ulate in to R0. SUBS R3,R3,#1 Decrement the coun ter. BNE LOOP Branch back if not done. STR R0,DOTPR OD Store dot pro duct. Figure 3.14. An ARM dot-product program.

  13. Figure 3.16. An ARM subroutine for inserting a new record in to a link ed list. Subroutine INSER TION CMP RHEAD,#0 Chec k if list empt y . MO VEQ RHEAD,RNEWREC If empt y , insert new MO VEQ PC,R14 record as head. LDR R0,[RHEAD] If not empt y , c hec k if LDR R1,[RNEWREC] new record b ecomes CMP R0,R1 new head, and STR GT RHEAD,[RNEWREC,#4] insert if y es. MO V GT RHEAD,RNEWREC MO V GT PC,R14 MO V R CURRENT,RHEAD If new record go es after LOOP LDR RNEXT,[R CURRENT,#4] curren t head, CMP RNEXT,#0 find where. STREQ RNEWREC,[R CURRENT,#4] New record b ecomes new tail. MO VEQ PC,R14 LDR R0,[RNEXT] Go further? CMP R0,R1 MO VL T R CURRENT,RNEXT Y es, then lo op bac k. BL T LOOP STR RNEXT,[RNEWREC,#4] Otherwise, insert new record STR RNEWREC,[R CURRENT,#4] b et w een curren t and MO V PC,R14 next records.

  14. Subroutine DELETION LDR R0,[RHEAD] Chec k if record to b e CMP R0,RIDNUM deleted is the head. LDREQ RHEAD,[RHEAD,#4] If y es, delete MO VEQ PC,R14 and return. MO V R CURRENT,RHEAD Otherwise, con tin ue searc h. LOOP LDR RNEXT,[RCURRENT,#4] Is next record the one LDR R0,[RNEXT] to b e deleted? CMP R0,RIDNUM LDREQ R0,[RNEXT,#4] If y es, delete STREQ R0,[R CURRENT,#4] and return. MO VEQ PC,R14 MO V R CURRENT,RNEXT Otherwise, lo op bac k B LOOP to con tin ue searc h. Figure 3.17. An ARM subroutine for deleting a record from a linked list.

  15. T ABLE 3.1 ARM index addressing modes Name Assembler syntax Addr essing function W ith immediate of fset: Pre-inde x ed [R n , #of fset] EA = [R n ] + of fset Pre-inde x ed with writeback [R n , #of fset]! EA = [R n ] + of fset;  R n [R n ] + of fset Post-inde x ed [R n ], #of fset EA = [R n ];  R n [R n ] + of fset W ith of fset magnitude in R m :   Pre-inde x ed [R n , R m , shift] EA = [R n ] [R m ] shifted Pre-inde x ed   with writeback [R n , R m , shift]! EA = [R n ] [R m ] shifted;   R n [R n ] [R m ] shifted  Post-inde x ed [R n ], R m , shift EA = [R n ];   R n [R n ] [R m ] shifted Relati v e Location EA = Location (Pre-inde x ed with = [PC] + of fset immediate of fset) EA = ef fecti v e address of fset = a signed number contained in the instruction shift = direction #inte ger where direction is LSL for left shift or LSR for right shift, and inte ger is a 5-bit unsigned number specifying the shift amount  R m = the of fset magnitude in re gister R m can be added to or subtracted from the contents of base re gister R n

  16. . . . T ABLE B.1 Condition field encoding in ARM instructions Condition Condition Name Condition co de field suffix test b b 31 28 0 0 0 0 EQ Equal (zero) Z = 1 0 0 0 1 NE Not equal (nonzero) Z = 0 0 0 1 0 CS/HS Carry set/Unsigned higher or same C = 1 0 0 1 1 CC/LO Carry clear/Unsigned lo w er C = 0 0 1 0 0 MI Min us (negative) N = 1 0 1 0 1 PL Plus (p ositiv e or zero) N = 0 0 1 1 0 VS Ov erflo w V = 1 0 1 1 1 VC No o v erflo w V = 0  1 0 0 0 HI Unsigned higher C Z = 0  1 0 0 1 LS Unsigned lo w er or same C Z = 1  1 0 1 0 GE Signed greater than or equal N V = 0  1 0 1 1 L T Signed less than N V = 1   1 1 0 0 GT Signed greater than Z (N V) = 0   1 1 0 1 LE Signed less than or equal Z (N V) = 1 1 1 1 0 AL Alw a ys 1 1 1 1 Not used

  17. T ABLE B.4 ARM instructions for single word or byte transfer from/to memory Mnemonic Instruction Operation (Name) bits p erformed B L  LDR 0 1 R d [EA] (Load w ord)  LDRB 1 1 R d [EA] (Load b yte)  STR 0 0 EA [R d ] (Store w ord)  STRB 1 0 EA [R d ] (Store b yte)

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