1 / 40

Team DC-HSBA

Team DC-HSBA. Robert Benson David Hover Jonathan Tate Paul Niewoonder. ROBERT BENSON. Primary Goal. Embedded Software Graphics Accelerator Shader Unit Media-Centric Co-Processor High Floating-Point Computation Performance Graphical Computation Complete Software Graphics Pipeline.

odessa
Download Presentation

Team DC-HSBA

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Team DC-HSBA Robert Benson David Hover Jonathan Tate Paul Niewoonder

  2. ROBERT BENSON

  3. Primary Goal • Embedded Software Graphics Accelerator • Shader Unit • Media-Centric Co-Processor • High Floating-Point Computation Performance • Graphical Computation • Complete Software Graphics Pipeline

  4. Hardware • Custom Multi-FPGA Development Board • Cyclone III FPGAs • Outputs • VGA Port • LEDs • Inputs • 8-Directional Joysticks • JTAG Programming Port

  5. Hardware Block Diagram

  6. Hardware Details • Abdomen • Cyclone III (EP3C16Q240C8) • DAC (ADV7123) • Serial Programming Device (EPCS) • JTAG Configuration Port • Leg • Cyclone III (EP3C25E144C7) • DDR SDRAM (512 MBit) • Ports for GPIO

  7. Hardware Details • I/O Widgets • 8 Directional Joystick • RGB LEDs • Communication Methods • Memory – DDR SSTL_2 • Inter FPGA - LVDS

  8. Hardware Power

  9. Cost Estimate

  10. Schematics?

  11. Layout?

  12. DAVID HOVER

  13. Software • User Application Software • Main User Interface • Benchmarks • Demos • Tetrisphere Clone • Graphics Pipeline Software • Assembler

  14. Main Menu See attached 

  15. Benchmarks & Demos • Benchmarks • Matrix Multiplications • Matrix-Vector Multiplications • Transcendental Function Calculation • Demos • Racecar • Bouncing Blob • Buffalo • Beach

  16. Software Implementation • “Game Loop” • Poll User Input • Update “Game” State • Redraw Environment • OpenDC API • Similar To OpenGL • Smaller Subset

  17. Example OpenDC Functions • State Manipulation • dcEnable() • dcClear() • dcFinish() • Matrix Manipulation • dcMatrixMode() • dcLoadIdentity() • Parameter Manipulation • dcBindShader() • dcBindTexture() • dcUniform1f()

  18. General Software Layout

  19. Graphics Pipeline Software • Hardware to Software Abstraction

  20. The Assembler - Flex • Matches expressions • Literal or regular expressions • Can perform any action after a match • The main task is to turn matches into tokens for the upcoming parser

  21. Flex (Cont.) Our Lexer has the following properties • Matches all valid assembly commands • Allows for comments, i.e, anything after a semicolon is ignored • Ignores all white space • Is able to distinguish between arguments and labels.

  22. The Assembler – Bison • Invoked after the lexer • Sends tokens through an annotated context-free grammar. • A context-free grammar, for example, has the form of: stmts : stmt stmts | stmt ; • This is one of many definitions. • This stores data as it parses

  23. Bison (Cont.) The parser is general, all commands are treated equally • Validity is checked per completed command • After completion, the parser passes the finished data to be converted into a bitstream

  24. JONATHAN TATE

  25. System Logic Design • Prebuilt • SOPC Builder • Memory Controllers • NIOS II Processor • Custom • Caches • LVDS to Avalon Interconnect Bridge • Shader Unit

  26. Shader ALU

  27. Shader Unit

  28. Leg Shader Block

  29. Shader Thread Scheduling

  30. Shader Thread Scheduling

  31. PAUL NIEWOONDER

  32. Arithmetic – Multiply-Add Multiply Unit

  33. Arithmetic – Multiply-Add Add Unit

  34. Arithmetic – Inverse Square Root float InvSqrt(float x) { float xhalf = 0.5f * x; int i = *(int*)&x; i = 0x5f3759d5 - (i >> 1); x = *(float*)&i; x = x*(1.5f - xhalf*x*x); return x; }

  35. Arithmetic – Divider • Chained subtract and bit shift • Requires many LUTs • Full divide support would take up most of the available board space • Limited divide support (1 divide per sixteen cycles)

  36. Case Design • Plexiglas substrate • Ventilation holes • Fan mount • Joystick control mount • VGA output port

  37. Schedule

  38. Milestone Deliverables • Milestone 1 • Revision 1 of Lobster FPGA Board • Iteration 1 of the Software • Milestone 2 • Lobster FPGA Board • Iteration 3 of the Software • All Logic • Capstone Expo • Crab FPGA Board

  39. Division of Labor • Jonathan Tate • System Logic Design • Shader Programs • Graphics Pipeline Control Software • David Hover • Assembler • User Application Software • Robert Benson • Board Design • User Application Software • Graphics Pipeline Control Software • Paul Niewoonder • Arithmetic Logic Design • Case

  40. QUESTIONS?

More Related