Performed by: Moti Mor Tomer Gal Instructor: Yaniv Ben-Itzhak

1. Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות דו”ח סיכום פרויקט סופי Subject: Heterogeneous Network on Chip Shared-Buffer Router Performed by: Moti Mor Tomer Gal Instructor: Yaniv Ben-Itzhak סמסטר חורף 2014 1

2. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Abstract Network-on-Chip (NoC) is a new approach to design the communication subsystem of System-on-a-Chip (SoC) and Chip-Multi-Processors (CMP). In order to overcome the BUS bottleneck in bus based communications in SoC, a new communication paradigm, network on chip (NoC) has been developed. In the NoC paradigm, the SoC modules communicate though a network of routers. Each router is connected to all its neighbors and to one of the SoC modules. The router IO port protocol is chosen according to the requirements of the application. NoC brings networking theories and systematic networking methods to on-chip communication and brings notable improvements over conventional bus systems. In this project, a Shared Buffer architecture was chosen, designed and implemented in the Heterogeneous NoC router system. The use of a Shared Buffer as a main buffering unit between the input ports and the output ports of each router allows to reduce the total number of buffers in the router and maximize the measurement: performance per power. 2

3. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System description The NoC is comprised of different heterogeneous routers, each router has various parameters which optimizes each router’s area and power consumption to it’s client needs in the network. Some of the heterogeneous parameters are: the number of virtual channels (VC), VCs’ depth, ports’ bandwidth, speed-up, number of shared buffers, etc. Incoming flits advanced across the router in a pipeline which includes the following stages: routing calculation, virtual channel allocation, time stamping, shared buffer allocation, shared buffer transition and link traversal. The router uses pointers to indicate each flit’s current stage in the pipeline while staying stationary in their input-buffers in order to optimize power consumption. All router’s in-ports use shared buffers as a shared resource, keeping the area requirement very low while maintaining a high throughput and performance. 3

4. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Specification • Hardware • Software • All units were written in VHDL. • Functional simulations were done in Mentor Graphics’Model-Sim 10.3 • Synthesis was done in Xilinx’s Vivado 2013.4 forVirtex-7 VC709 Evaluation Platform board 4

5. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System Block Diagram 5

6. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Synthesis Diagram Routing ControlUnit: InputBuffer: Virtual Channel Allocator: OutportsUnit: Shared Buffer Allocator: 6