EE434 ASIC & Digital Systems

1. EE434ASIC & Digital Systems Jacob Murray School of EECS Washington State University jmurray@eecs.wsu.edu

2. Digital Design with VHDL Lecture 14

3. State Machine Design • A simple memory controller • The controller enables or disables the write enable (we) and output enable (oe) signals. • Signals ready andread_writeare outputs of a microprocessor and inputs to the controller. • A new transaction begins with the assertion of the ready following a completed transaction. • One cycle after the commencement of a transaction, the value of read_write determines whether it is a read or write transaction. • A cycle is completed by the assertion of ready.

4. State Diagram

5. State Machines in VHDL • Define an enumeration type, consisting of state names • Declare two signals of that type to hold the current and next state type statetype is (idle, decision, read, write); signal present_state, next_state : statetype; • Create a process, within that processnext_stateis determined by a function of the present_stateand the inputs (readyand read_write) • This process should be sensitive to these signals.

6. State Transition Process state_comb : process (present_state, read_write, ready) begin case present_state is when idle => oe <= ‘0’; we <= ‘0’; if ready = ‘1’ then next_state <= decision; else next_state <= idle; end if; ……………

7. Two-state FSM The state transition happens synchronously state_clocked: process (clk) begin if (clk ‘eventand clk = ‘1’) then present_state <= next_state; end if; end process state_clocked;

8. Reset in State Machine

9. Reset in State Machine (cont’d) if-then-else statement at the beginning of the process state_comb : process (present_state, read_write, ready) begin if (reset=‘1’) then oe <= ‘-’; we <= ‘-’; next_state <= idle; else case present_state is ---------- end case end if; end process;

10. Asynchronous Reset my_state: process (clk, reset) begin if reset = ‘1’ then present_state<=idle; elsif rising_edge (clk) then present_state <= next_state; end if; end process;

11. Output Decoding Inputs Outputs State variable ‘present_state’ is represented by a bit_vector (0 to 2) State encoding (sequential) for present_state is idle := b”000”; decision := b”001”; ……… Outputs decoded from state bits combinatorially – Moore Machine

12. Output Decoding (cont’d) Outputs Inputs Outputs decoded in parallel output registers

13. Output Decoding (cont’d) Inputs Outputs signal state : std_logic_vector (4 downto 0); constant idle : std_logic_vector (4 downto 0) := “00000”; constant decision : std_logic_vector (4 downto 0) := “00001”; ……………

14. Outputs encoded with state registers state_tr: process (reset, clk) begin if reset = ‘1’ then state <= idle; elsif rising_edge (clk) then case state is when idle => if (bus_id = “11110011”) then state <= decision; end if; ………… end case …… we <= state (1); oe <= state (2); ………

15. One-Hot Encoding • n flip-flops to represent a state machine with n states • Each state has its own flip-flop • At any given time only one flip flop is hot (holds a 1) • Number of gates needed to decode state information is less type statetype is (idle, decision,…….) attribute state_encoding of statetype : type is one_hot_one;

16. Generating output in one-hot machine • Outputs decoded from state registers • States are just single bits • The output logic will have a OR gate only • Output decoding adds a level of combinational logic

17. Mealy Machines Outputs are functions of present-state and present-input signals if (current_state = s6) and (write_mask = ‘0’) then we <= ‘1’; else ……

18. Fault Tolerance: An Example type statetype is (idle, decision, read1, read2, read3, read4, write); • Enumeration types provides an easy way • When synthesized, state signals are converted to vectors internal to the tool. • Each value of the state type is assigned an encoding • Using sequential encoding, state will require three flip-flops

19. Implicit Don’t-Cares • Synthesis will assume that the value of 111 for q is “don’t-care”. • Transitions into or out of this state are not defined. • Could be a source of unpredictable design behavior.

20. Explicit Don’t Cares State machines with explicit state encoding type statetype is (idle, decision, read1, read2, read3, read4, write, undefined); case present_state is …………. when undefined => next_state<= idle; end case; ……………… when others => next_state <= idle; ……………… when others => next_state <= ‘---’;

21. Generic Constants Parameterized models component register_n is generic (width: integer :=8); port ( clk, rst, en : in std_logic; data : in std_logic_vector (width-1 downto 0); q : out std_logic_vector (width-1 downto 0)); end component;

22. Component Instantiation with Generics

23. Mapping Generic Values

24. Configuration Declaration • Bindings of entities to architectures • A configuration specifies one combination of an entity and its associated architecture architecture struct of reg4 is component flipflop generic (Tprop, Tsetup, Thold : delay_length); port (clk, clr, d : in bit; q : out bit); end component flipflop; begin bit0: component flipflop generic map (Tprop=>2 ns, Tsetup=>2ns, Thold=>1ns) port map (clk=>clk, clr=>clr, d=>d(0), q=>q(0)); bit1:……. bit2:....... bit3:…….

25. Configuration Declaration (Cont’d) configuration reg4_gate_level of reg4 is for struct for bit0: flipflop use entity edge_triggered_Dff (hi_fanout); end for; for others: flipflop use entity edge_triggered_Dff (basic); end for; end for; end configuration reg4_gate_level;