Critical Signal Flow for Power Estimation: The Road to Billion Gate SoC Power Verification

1. Critical Signal Flow for Power Estimation: The Road to Billion Gate SoC Power Verification Chungki Oh, Jianfeng Liu, Seokhoon Kim, Kyung-Tae Do, JungYunChoi, Hyo-Sig Won, Kee Sup Kim • Design Technology Team • System LSI Division • Samsung Electronics • Jeongwon Kang, Kamlesh Madheshiya, Arti Dwivedi Ansys Apache

2. Table of Contents • Mobile SoC Design Trend • Challenges in SoC Power Analysis • Power Critical Signal Flow in RTL/Gate power analysis • Summary

3. Mobile SoC Design Trend • The design size of mobile SoC has been increasing at a rapid speed • Fierce competition in mobile market has driven SoC design to provide high performance and numerous functionality, which was only previously available in PC and laptop • To meet the power wall of mobile design and leverage the additional capacity in silicon processing scaling, multiple cores and parallelism are popular in current SoC design Billion Gate SoC SoC consumer portable design complexity trends - ITRS, 2011 edition

4. Challenges in SoC Power Analysis • The era of billion gate SoC design put significant challenges for power analysis • Simulation is needed to analyze the dynamic power accurately. However, for billion gate SoC, the simulation runtime is becoming too long for reasonable design cycle • The simulation waveform generated from simulation can occupy more than hundreds of GigaBytes, which puts significant burden on power analysis tools to deal with. 10’s of modes Video streaming . . . . GPS + Voice Call Web + Email Millions of clocks

5. RTL Power Estimation Flow • Basic concept of RTL power estimation Inputs: RTL-coded design, power library, capacitance model, activity file • Elaborate: RTL design is compiled and elaborated into an interconnection of primitive gates • Calculate Power: Design is mapped to the target technology and average/time-based power analysis is performed based on switching activity RTL (Verilog/VHDL) Power Library (.lib) Capacitance model PowerArtist Verilog Simulation Elaborate Activity File (.vcd/.fsdb/.saif) Micro-architectural Inferred netlist Calculate Power RTL power report To obtain reasonable accuracy, simulation is needed for vector-based power estimation

6. Critical Signal Extraction with PowerArtist • Generate a significantly smaller power-critical-signals-only FSDB from the Emulator/Simulator RTL Test Bench RTL Verilog Simulation PowerArtist Power-Critical Signal Extraction Critical Signal List Test Bench initial befin $fsdbDumpfile(“pa_extracted.fsdb”); $fsdbDumpvarsByFile(“sig_file_name”); end Full FSDB Verilog Simulation testbench.top_inst.temp_out testbench.top_inst.temp testbench.top_inst.en testbench.top_inst.out testbench.top_inst.clk testbench.top_inst.inC testbench.top_inst.inB testbench.top_inst.inA Partial FSDB

7. Power-Critical Functional-Debug Signals Optimized for power analysis over entire simulation duration Functional Debug Tools L2 Simulator/Emulator Identify Function-Critical Signals Functional Debug Reduced FSDB Optimized for functional debug over limited clock cycles Apache PowerArtist L1 Simulator/Emulator Identify Power-Critical Signals Power Analysis + Debug Reduced FSDB

8. The Principle of Power-Critical Signal Flow • Power-critical signals • Activity for only a subset of signals is necessary for accurate power estimation • Critical signals consists of signals such as sequential and module in/out ports • Non-critical signals • Activity propagation can be performed for the remaining signals based-on activity propagation formulae of various cell types IO cells PI & PO Latches ICGCs Flip-Flops MUX

9. Power-Critical Signal Flow with PowerArtist • Application • Power-critical signals can be extracted for both RTL and gate-level designs • Critical signals can be utilized in simulation as well as emulation flows • Impact • Activity file dumped only for power-critical signals saves simulator/emulator and power analysis runtime and memory resource with small error in power analysis • Power-critical signal flow enables power analysis of huge design for which power estimation used to be unrealizable Wire Load Model Power Library RT/Gate-level design Crit. Sig. Extraction Elaborate PowerArtist Crit. sig. list Test Bench Micro-architecturally Inferred netlist Time & Memory Saving Simulation/Emulation Time & Memory Saving Partially dumped Activity File Calculate Power RTL Power Report

10. Critical Signal Flow for RTL Power Estimation • Experimental result with Design-A in RTL • The first experiment was done with a multimedia codec IP design • Design size is about 8 Million Gates, with 32nm library Impact on memory resource & power result Impact on CPU time 46% Memory saving 58% Disk saving 69% Time reduction 5% Power mismatch CPU time

11. Critical Signal Flow for RTL Power Estimation (2) • Experimental result with Design-B in RTL • The second experiment was done with quad-core CPU block • Design size is Tens of Million Gates, with 32nm library Impact on CPU time Impact on memory resource & power result 42% Memory saving 73% Disk saving 78% Time reduction 2% Power mismatch 117 CPU time [hr] 12 24 14

12. Critical Signal Flow for Gate-level Power Estimation • Experimental result with Design-A in Gate-level • The third experiment was done with same design as the first one but in gate-level • Design size is about 8 Million Gates, with 32nm library Impact on CPU time Impact on memory resource & power result 87% Memory saving 97% Disk saving 69% Time reduction 9% Power mismatch CPU time

13. Summary • In the era of billion gate SoC chip design, the runtime and generated waveform database size are challenging issues for accurate power estimation. • To solve this challenge, we have proposed to use a subset of the full signal list in the design when dumping the waveform. We have introduced the methodology on how to choose this signal subset for good power correlation while keep this signal subset small enough. • The PowerArtist power critical signal flow has been verified by extensive experiments covering both RTL and gate-level power estimation flows. • Our experimental results show that critical signal flow cut the runtime by 70-80%, simulation waveform size by 60-97%, while keeping the power correlation within less 10%mismatch.