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Dynamic Reduction of Voltage Margins by Leveraging On-chip ECC in Itanium II Processors

Dynamic Reduction of Voltage Margins by Leveraging On-chip ECC in Itanium II Processors. Presented By : SOMESH PAL (13IS23F)

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Dynamic Reduction of Voltage Margins by Leveraging On-chip ECC in Itanium II Processors

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  1. Dynamic Reduction of Voltage Margins by Leveraging On-chip ECC in Itanium II Processors Presented By : SOMESH PAL (13IS23F) VISHAL BABU (13IS25F) MTECH CSE-IS NITK SURATHKAL Anys Bacha Computer Science and Engineering The Ohio State University bacha@cse.ohio-state.edu Radu Teodorescu Computer Science and Engineering The Ohio State University teodores@cse.ohio-state.edu Under Guidance Of : Dr. BasvarajTalawar Assistant professor, Dept. of CSE, NITK

  2. CONTENTS: • Introduction • Motivation • ECC-Based voltage speculation • Prototype Implementation • Evaluation Methodology • Evaluation • Related Work • Conclusion and Future Work

  3. Introduction : • Dynamically reducing voltage margins & lowering vddwhile chip operating frequency constant. • Firmware-based technique for voltage speculation. • On-chip correctable error report to identify lowest, safe operating voltage. • Evaluates a prototype implementation of the voltage speculation system on an HP server using Intel's Itanium 9560 processors.

  4. Motivation • Supply voltage depends on: • Design process • such as speed, power consumption etc. • Run time environment • it includes temperature variation, circuit aging etc.

  5. Motivation • Experiments on Intel Itanium II 9560 8-core processors: • Chip frequency was set at their nominal values according to the product specifications. • The Vdd was gradually lowered for each core while running a stress test workload until system crashes or data corruption occur. • The lowest safe voltage at which each core runs reliably is recorded. • Voltages that are significantly lower than nominal values – 12% lower on average.

  6. Motivation

  7. Motivation • Results of experiments: • Record correctable error report flagged by the hardware. • They are single-bit errors that occur in ECC-protected functional units. • The ECC hardware corrects these errors and logs them for debugging purposes. • When the Vdd of the core is lowered below 0.96V, the system no longer operates reliably.

  8. Motivation

  9. ECC-Based voltage speculation: • Our solution has two main components: • Error monitoring system : for identifying and logging correctable errors • Dynamic voltage speculation governor:for dynamically controlling Vdd. • This paper present a new voltage speculation system that dynamically lowers Vdd and uses correctable error reports to ensure cores do not reach unsafe operating levels. • In general correctable error handling, as implemented in current processors is invisible to the Operating System (OS) and the applications running on the system. • Our system taps into correctable error logs by configuring the hardware to report correctable errors to a firmware layer that implements our monitoring functions.

  10. Margin Voltage Discovery:

  11. Aggressive vs. Conservative Cores:

  12. Dynamic Voltage Speculation: • A firmware-based Voltage Speculation Governor . • The governor receives input from the error monitoring system and reacts to information about error rates according to predefined algorithms. • The governor is also responsible for coordinating the margin voltage discovery phase. • Aggressive and conservative cores are handled differently by the voltage speculation algorithms. • So this Dynamic Voltage Speculation work in two parts • 1. Conservative Speculation • 2. Aggressive Speculation

  13. Conservative Speculation :

  14. Conservative Speculation : • Conservative cores are more vulnerable to low-voltage operation. • To ensure correct execution, we add a small safety padding • when computing their margin voltage. Conservative cores are never allowed to run below the margin voltage • if correctable errors occur the governor raises its Vdd in increments of 10 mV per correctable error • If no error is observed for a while, the governor attempts to lower the Vdd again in 5 mV decrements after every minute • Decrementing the voltage continues until the margin voltage is reached again.

  15. Aggressive Speculation:

  16. Aggressive Speculation: Aggressive cores can, in many cases, operate below the margin voltage. The Voltage Speculation Governor gradually lowers Vdd below the margin as long as the error rate remains below the Max error threshold. In our implementation, that threshold is 1 error per minute Once that threshold is reached, the governor will maintain a constant Vdd and continue to monitor the error rate Aggressive speculation ends if any of the following events occur: Correctable error rate exceeds the Max error thresh- old indicating approaching timing margins. Correctable error rate is below the Min error threshold. A context switch is signaled by the OS indicating the need to reevaluate suitability for aggressive speculation

  17. Aggressive Speculation: aggressive core running the stress test workload

  18. Prototype Implementation:

  19. PrototypeImplementation • The proposed voltage speculation system was prototyped on an HP Integrity Server that uses Intel’s Itanium 9560 processors • There are two layers • Processor Abstraction Layer (PAL) : • it is interface between SAL(System Abstraction Layer) and hardware power management, error record extraction. • it provides hooks for communicating with the rest of System Firmware via architected entry- points. • Our solution mainly uses PAL calls for extracting and clearing error information generated by the processor hardware. • System Abstraction Layer (SAL): • main layer • There are two module in SAL • Error Monitor for Margin Detection • Voltage Speculation Governor

  20. References 1) Dynamic Reduction of Voltage Margins by Leveraging On-chip ECC in Itanium II Processors ISCA ’13 Tel-Aviv, Israel. 2) H. Ando, K. Seki, S. Sakashita, M. Aihara, Kan, and K. Imada. Accelerated testing of a 90nm SPARC64 V microprocessor for neutron SER. IEEE Workshop on Silicon Errors in Logic - System Eects (SELSE),2007. Z. Chishti, A. R. Alameldeen, C. Wilkerson, W. Wu, and S.-L. Lu. Improving cache lifetime reliability at ultra-low voltages. In International Symposium on Micro architecture (MICRO), December 2009. 4) J. Donald and M. Martonosi. Power eficiency for variation-tolerant multicore processors. In International Symposium on Low Power Electronics and Design (ISLPED), pages 304{309, October 2006. 5) J. Dorsey, S. Searles, M. Ciraula, S. Johnson, N. Bujanos, D. Wu, M. Braganza, S. Meyers, E. Fang, and R. Kumar. An integrated quad-core Opteron processor. In International Solid-State Circuits Conference (ISSCC), pages 102{103, February 2007 .

  21. THANK YOU

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