Viterbi Decoder: Presentation #3

1. Overall Project Objective: Design of a high speed Viterbi Decoder Stage 3: 2 Feb. 2004 Size Estimates/ Floorplan Viterbi Decoder: Presentation #3 M1 Omar Ahmad Prateek Goenka Saim Qidwai Lingyan Sun Design Manager: Yaping Zhan

2. Status • Design Proposal (finalized) • Architecture Proposal (done) • Behavioral -> Structural Verilog (done) • Floor-planning and size estimates (done) • To be done: • Schematics of Design (20% done) • Component Layout • Chip Layout • Spice Simulation of Entire Chip 18-525, Integrated Circuits Design Project

3. Design Decisions: Metal Directionality M1 Metal usage: Vdd! – M1, M2 Gnd! – M1, M2 Internal Routing – M1, M2 Clock – M3, M4 Reset – M3, M4 Global Routing – M3, M4 M2 M4 M3 18-525, Integrated Circuits Design Project

4. Design Decisions: Adders Ripple-carry Vs. Carry look-ahead • 5 gates/bit • ~34 transistors/bit • For 8 bits ~ 40 gates • Easy to implement • Slightly faster • Harder logic • Too big ~ 35 gates/4 bits • ~14,000 transistors • for all adders in design Decision? Ripple-carry chosen & used Mirror Adders ~28 transistors/bit 18-525, Integrated Circuits Design Project

5. Design Decisions: Simpler Multiplier Chosen 18-525, Integrated Circuits Design Project

6. Design Decisions: Trace back unit Place each flip-flop & mux pair like this? Chosen Or like this? Too long 18-525, Integrated Circuits Design Project

7. Design Decisions: Dealing with Clock skew Possible ideas: • Tapering • Buffering • H-Tree Clock 18-525, Integrated Circuits Design Project

8. Floor Plan: Top Level Sizing 650 BCU Unit 40 650 ACS Unit 70 250 170 ML Search TB Unit 70 140 All units in microns 18-525, Integrated Circuits Design Project

9. Floor Plan: Top Level Routing 650 clk BCU Unit ACS Unit rst Buffering/Routing 350 ML Search TB Unit All units in microns 18-525, Integrated Circuits Design Project

10. Floor Plan: Branch Calculation Unit 650 Flip Flops Flip Flops …………………….. 40 All units in microns 18-525, Integrated Circuits Design Project

11. Floor Plan: Add Compare Select Unit 650 Flip Flop Flip Flop ……………………. Adder Adder ……………………. Subtractor Subtractor 70 Mux ……………………. Mux Flip Flop Flip Flop ……………………. All units in microns 18-525, Integrated Circuits Design Project

12. Floor Plan: ML Search 8 Bit Subtractor 8 Bit Subtractor 8 Bit Subtractor 8 Bit Subtractor 8 Bit Mux + Flop 8 Bit Mux + Flop 8 Bit Mux + Flop 8 Bit Mux + Flop 3 Bit Mux + Flop 3 Bit Mux + Flop 8 Bit Subtractor 8 Bit Subtractor 3 Bit Mux + Flop 3 Bit Mux + Flop 8 Bit Mux + Flop 8 Bit Mux + Flop 3 Bit Mux + Flop 3 Bit Mux + Flop 8 Bit Subtractor 3 Bit Mux + Flop 140 250 All units in microns 18-525, Integrated Circuits Design Project

13. Floor Plan: Trace Back Unit Dff Dff Dff Dff …… Mux Mux Mux Mux 70 …………………………………………………. Dff Dff Dff Dff …… 170 All units in microns 18-525, Integrated Circuits Design Project

14. New Transistor Counts Branch Calculation Unit: D-Flip Flops 4 x 17 x 12 + 8 x 16 x 12 = 2,352 Adders 4 x 16 x 28 = 1,792 8 bit Multipliers 16 x 150 = 2,400 Total 6,544 Add Compare Select Unit: D-Flip Flops 8 x 24 x 12 + 1 x 8 x 12 = 2,400 2:1 Multiplexers 8 x 8 x 14 = 896 Adders 8 x 16 x 28 = 3,584 Subtracters 8 x 8 x 29 = 1,856 Total 8,736 Grand Total = 22,402! Maximum Likelihood Search Unit: D-Flip Flops 8 x 6 x 12 + 3 x 7 x 12 = 828 2:1 Multiplexers 8 x 6 x 14 + 3 x 7 x 14 = 966 Comparators 8 x 7 x 32 = 1,792 Adders 4 x 1 x 28 = 112 Total 3,698 Trace Back Unit: D-Flip Flops 8 x 17 x 12 = 1,632 2:1 Multiplexers 8 x 16 x 14 = 1,792 Total 3,424 Key: No. of bits x No. of elements x No. of transistors/bit

15. Transistor CountsPrevious Vs. Revised Previous Revised 5,900 1,056 3,840 2,400 14,196 Adders 2:1 Multiplexers Multipliers Registers Total 9,136 3,654 2,400 7,212 22,402 18-525, Integrated Circuits Design Project

16. Structural Verilog 18-525, Integrated Circuits Design Project

17. Structural Verilog Simulation 18-525, Integrated Circuits Design Project

18. Questions? 18-525, Integrated Circuits Design Project