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April 3rd, 2007

Update of the “Digital EMC project”. April 3rd, 2007. Junfeng Zhou Promotor: Prof. Wim Dehaene KULeuven ESAT-MICAS. EME and di/dt measurement Setups. Setup-3. Setup-2. Setup-1. VCCC =12 V. VCC = 4.5 V ~ 8 V. VDD2 = 3.3 V. i 2. i 3. i 1. EMI-Suppressing Regulator (MICAS).

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April 3rd, 2007

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  1. Update of the “Digital EMC project” April 3rd, 2007 Junfeng Zhou Promotor: Prof. Wim Dehaene KULeuven ESAT-MICAS

  2. EME and di/dt measurement Setups Setup-3 Setup-2 Setup-1 VCCC =12 V VCC = 4.5 V ~ 8 V VDD2 = 3.3 V i2 i3 i1 EMI-Suppressing Regulator (MICAS) VDD<1..10> Low Drop-out / Serial Regulator AMIS digital load VCC i5 and V2 GND i4 and V1 configuration bits Automatic setup is ready both for time and frequency domain ! PC

  3. Setup-1 – EME as function of Gate Account Scenario 1 48dBuV Neighbouring DFFs in the chain are directly connected 46dBuV 43dBuV Scenario 2 9 inverters between neighbouring DFFs + one inverter chain Scenario 3 9 inverters between neighbouring DFFs + one inverter chain + the other two inverter chain Clk=8 MHz in all scenarios Data is random

  4. Description of the gate account comparison DFFs are connected directly Out Din CLK RST FF FF FF FF 60 FF 9 inverters The other two inverter chains

  5. Setup-1 – di/dt as function of Gate Account di/dtPk-Pk=1.4 x107 A/s di/dtPk-Pk= 5 x106 A/s di/dtPk-Pk=6 x106 A/s

  6. Setup-1 – EME as function of Clock Frequency 51dBuV 46dBuV 44dBuV Clock=5 MHz Clock=2.5 MHz Clock=10 MHz All these three measurements are based on Scenario 3 Data is random

  7. Setup-1 – di/dt as function of Clock Frequency Clock=10 MHz Clock=5 MHz Clock=2.5 MHz di/dtPk-Pk=1.1 x107 Amp/s di/dtPk-Pk= 7.2 x106 Amp/s di/dtPk-Pk=1.4 x106 Amp/s Not explained, why peak= F(frequency) ?

  8. Setup-1 – EME as function of Supply voltage VDD=3.3 V VDD=2.0 V VDD=1.5 V 51dBuV 46dBuV All these three measurements are based on Scenario 3 36dBuV Data is random

  9. Setup-1 – di/dt as function of Supply voltage VDD=1.5 V VDD=2.0 V VDD=3.3 V di/dtPk-Pk=1.1 x107 Amp/s di/dtPk-Pk=1.4 x106 Amp/s di/dtPk-Pk= 3.1 x106 Amp/s

  10. The effectiveness of EMI-SR and SR - EME Setup-1: Directly 3.3 V supply Setup-2: Series Regulator Setup-3: EMI-Suppressing Reg + Series Reg 53dBuV 42dBuV All these three measurements are based on Scenario 3 22dBuV Data is periodic Clk=8 MHz

  11. The effectiveness of EMI-SR and SR – di/dt di/dtPk-Pk=2 x107 A/s di/dtPk-Pk= 2.9 x106 A/s di/dtPk-Pk=1.1 x106 A/s Setup-1: Directly 3.3 V supply Setup-2: Series Regulator Setup-3: EMI-Suppressing Regulator + Series Regulator See previous slides for detail setup

  12. Future Work • Continue the digital load measurements, • Interpretation of the measured results • More analysis for new structure: • Stability and Transient, • Spice simulation.

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