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Deer Park Heights, Looking Down on Lake Wakatipu and Queenstown

Deer Park Heights, Looking Down on Lake Wakatipu and Queenstown. Deer Park Heights, Looking at the Remarkables (Rohan). 332:479 Concepts in VLSI Design Lecture 3 The VLSI Transistor and CMOS Fabrication. David Harris and Michael Bushnell Harvey Mudd College and Rutgers University Spring 2004.

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Deer Park Heights, Looking Down on Lake Wakatipu and Queenstown

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  1. Concepts in VLSI Des. Lec. 3 Deer Park Heights, Looking Down on Lake Wakatipu and Queenstown

  2. Concepts in VLSI Des. Lec. 3 Deer Park Heights, Looking at the Remarkables (Rohan)

  3. 332:479 Concepts in VLSIDesignLecture 3The VLSI Transistor and CMOS Fabrication David Harris and Michael Bushnell Harvey Mudd College and Rutgers University Spring 2004

  4. Outline • nMOS transistor • pMOS transistor • CMOS Inverter • Elementary Logic Gates • Chip fabrication • Design Rules • Layout • Summary Material from: CMOS VLSI Design, by Weste and Harris, Addison-Wesley, 2005 Concepts in VLSI Des. Lec. 3

  5. Transistor and IC History • MOSFET idea: • J. Lilienfeld 1925 • O. Heil 1935 • Experiments in early Field-Effect Transistor (FET) failed due to material problems • Led to invention of Bipolar transistor at Bell Telephone Laboratories in 1947 by Shockley, Brittain, and Bardeen – 1956 Nobel Prize in Physics Concepts in VLSI Des. Lec. 3

  6. CMOS MOSFET Inventions • Key Patents: • P.K. Weimer – Radio Corporation of America (RCA) 1962 – CMOS Flip-Flop Implementation • Frank Wanlass – Fairchild 1963 – CMOS Logic Gates • Two types of MOS transistors Concepts in VLSI Des. Lec. 3

  7. Introduction • Integrated circuits: many transistors on one chip. • Very Large Scale Integration (VLSI): very many • Complementary Metal Oxide Semiconductor • Fast, cheap, low power transistors • Today: How to build your own simple CMOS chip • CMOS transistors • Building logic gates from transistors • Transistor layout and fabrication • Rest of the course: How to build a good CMOS chip Concepts in VLSI Des. Lec. 3

  8. Silicon Lattice • Transistors are built on a silicon substrate • Silicon is a Group IV material • Forms crystal lattice with bonds to four neighbors Concepts in VLSI Des. Lec. 3

  9. Dopants • Silicon is a semiconductor • Pure silicon has no free carriers and conducts poorly • Adding dopants increases the conductivity • Group V: extra electron (n-type) • Group III: missing electron, called hole (p-type) Concepts in VLSI Des. Lec. 3

  10. p-n Junctions • A junction between p-type and n-type semiconductor forms a diode. • Current flows only in one direction Concepts in VLSI Des. Lec. 3

  11. nMOS Transistor • Four terminals: gate, source, drain, body • Gate – oxide – body stack looks like a capacitor • Gate and body are conductors • SiO2 (oxide) is a very good insulator • Called metal – oxide – semiconductor (MOS) capacitor • Even though gate is no longer made of metal Concepts in VLSI Des. Lec. 3

  12. nMOS Operation • Body is commonly tied to ground (0 V) • When the gate is at a low voltage: • P-type body is at low voltage • Source-body and drain-body diodes are OFF • No current flows, transistor is OFF Concepts in VLSI Des. Lec. 3

  13. nMOS Operation (cont’d.) • When the gate is at a high voltage: • Positive charge on gate of MOS capacitor • Negative charge attracted to body • Inverts a channel under gate to n-type • Now current can flow through n-type silicon from source through channel to drain, transistor is ON Concepts in VLSI Des. Lec. 3

  14. pMOS Transistor • Similar, but doping and voltages reversed • Body tied to high voltage (VDD) • Gate low: transistor ON • Gate high: transistor OFF • Bubble indicates inverted behavior Concepts in VLSI Des. Lec. 3

  15. Power Supply Voltage • GND = 0 V • In 1980’s, VDD = 5V • VDD has decreased in modern processes • High VDD would damage modern tiny transistors • Lower VDD saves power • VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, … Concepts in VLSI Des. Lec. 3

  16. Transistors as Switches • We can view MOS transistors as electrically controlled switches • Voltage at gate controls path from source to drain Concepts in VLSI Des. Lec. 3

  17. CMOS Inverter Concepts in VLSI Des. Lec. 3

  18. CMOS Inverter Concepts in VLSI Des. Lec. 3

  19. CMOS Inverter Concepts in VLSI Des. Lec. 3

  20. CMOS NAND Gate Concepts in VLSI Des. Lec. 3

  21. CMOS NAND Gate Concepts in VLSI Des. Lec. 3

  22. CMOS NAND Gate Concepts in VLSI Des. Lec. 3

  23. CMOS NAND Gate Concepts in VLSI Des. Lec. 3

  24. CMOS NAND Gate Concepts in VLSI Des. Lec. 3

  25. CMOS NAND Gate Concepts in VLSI Des. Lec. 3

  26. CMOS NOR Gate Concepts in VLSI Des. Lec. 3

  27. CMOS NOR Gate Concepts in VLSI Des. Lec. 3

  28. 3-input NAND Gate • Y pulls low if ALL inputs are 1 • Y pulls high if ANY input is 0 Concepts in VLSI Des. Lec. 3

  29. 3-input NAND Gate • Y pulls low if ALL inputs are 1 • Y pulls high if ANY input is 0 Concepts in VLSI Des. Lec. 3

  30. CMOS Fabrication • CMOS transistors are fabricated on silicon wafer • Lithography process similar to printing press • On each step, different materials are deposited or etched • Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process Concepts in VLSI Des. Lec. 3

  31. Inverter Cross-section • Typically use p-type substrate for nMOS transistors • Requires n-well for body of pMOS transistors Concepts in VLSI Des. Lec. 3

  32. Well and Substrate Taps • Substrate must be tied to GND and n-well to VDD • Metal to lightly-doped semiconductor forms poor connection called Shottky Diode • Use heavily doped well and substrate contacts / taps Concepts in VLSI Des. Lec. 3

  33. Inverter Mask Set • Transistors and wires are defined by masks • Cross-section taken along dashed line Concepts in VLSI Des. Lec. 3

  34. Detailed Mask Views • Six masks • n-well • Polysilicon • n+ diffusion • p+ diffusion • Contact • Metal Concepts in VLSI Des. Lec. 3

  35. Fabrication Steps • Start with blank wafer • Build inverter from the bottom up • First step will be to form the n-well • Cover wafer with protective layer of SiO2 (oxide) • Remove layer where n-well should be built • Implant or diffuse n dopants into exposed wafer • Strip off SiO2 Concepts in VLSI Des. Lec. 3

  36. Oxidation • Grow SiO2 on top of Si wafer • 900 – 1200 C with H2O or O2 in oxidation furnace Concepts in VLSI Des. Lec. 3

  37. Photoresist • Spin on photoresist • Photoresist is a light-sensitive organic polymer • Softens where exposed to light Concepts in VLSI Des. Lec. 3

  38. Lithography • Expose photoresist through n-well mask • Strip off exposed photoresist Concepts in VLSI Des. Lec. 3

  39. Etch • Etch oxide with hydrofluoric acid (HF) • Seeps through skin and eats bone; nasty stuff!!! • Only attacks oxide where resist has been exposed Concepts in VLSI Des. Lec. 3

  40. Strip Photoresist • Strip off remaining photoresist • Use mixture of acids called piranah etch • Necessary so resist doesn’t melt in next step Concepts in VLSI Des. Lec. 3

  41. n-Well • n-well is formed with diffusion or ion implantation • Diffusion • Place wafer in furnace with arsenic gas • Heat until As atoms diffuse into exposed Si • Ion Implanatation • Blast wafer with beam of As ions • Ions blocked by SiO2, only enter exposed Si Concepts in VLSI Des. Lec. 3

  42. Strip Oxide • Strip off the remaining oxide using HF acid • Back to bare wafer with n-well • Subsequent steps involve similar series of steps Concepts in VLSI Des. Lec. 3

  43. Polysilicon • Deposit very thin layer of gate oxide • < 20 Å (6-7 atomic layers) • Chemical Vapor Deposition (CVD) of silicon layer • Place wafer in furnace with Silane gas (SiH4) • Forms many small crystals called polysilicon • Heavily doped to be good conductor Concepts in VLSI Des. Lec. 3

  44. Polysilicon Patterning • Use same lithography process to pattern polysilicon Concepts in VLSI Des. Lec. 3

  45. Self-Aligned Process • Use oxide and masking to expose where n+ dopants should be diffused or implanted • N-diffusion forms nMOS source, drain, and n-well contact Concepts in VLSI Des. Lec. 3

  46. n-Diffusion • Pattern oxide and form n+ regions • Self-aligned process where gate blocks diffusion • Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing Concepts in VLSI Des. Lec. 3

  47. n-Diffusion (cont’d.) • Historically dopants were diffused • Usually ion implantation today • But regions are still called diffusion Concepts in VLSI Des. Lec. 3

  48. n-Diffusion (cont’d.) • Strip off oxide to complete patterning step Concepts in VLSI Des. Lec. 3

  49. p-Diffusion • Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact Concepts in VLSI Des. Lec. 3

  50. Contacts • Now we need to wire together the devices • Cover chip with thick field oxide • Etch oxide where contact cuts are needed Concepts in VLSI Des. Lec. 3

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