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ECE 4110– Sequential Logic Design. Lecture #2 Agenda Logic Design Tools Announcements n/a. Logic Design Tools.
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ECE 4110– Sequential Logic Design Lecture #2 • Agenda • Logic Design Tools • Announcements • n/a
Logic Design Tools • MS Visio- a generic drawing program.- industry is converging on this program for documentation.- has built in shape libraries, including analog/digital logic.- we’ll use it for this class to create clean schematics.
Logic Design Tools • MS Visio Predefined Shapes
Logic Design Tools • ModelSim (by Mentor Graphics)- an HDL Simulation (VHDL and Verilog)- widely used in industry- has color-coded text editing for keywords- has console for verification reporting- we’ll use for homework & before FPGA synthesis.
Logic Design Tools • ModelSim Simulation Waveform ProjectNavigator Console
Logic Design Tools • ModelSim Text Editor
Logic Design Tools • Xilinx ISE - Integrated Software Environment (ISE)- Implementation tool - compile / simulate- synthesis- technology mapping- place and route- back annotation for post-route simulation and timing verification- can do similar simulation as in ModelSim- this is where we : - select FPGA to target - assign signal pins - set timing constraints - set placement constraints - set routing constraints - generate programming file - download file to FPGA, EEprom, or CPLD using the JTAG interface.
Logic Design Tools • Xilinx ISE SourcesWindow Edit/ViewWindow ProcessesWindow
Logic Design Tools • Xilinx ISE ResourceUsage PackageView Pin Assignments
Logic Design Tools • Xilinx ISE RoutingEditor HDL or Schematic Entry
Assignment > Pins For example, SW0,SW1 are connected on FPGA Pins N25,N26. LEDG0 is pin AE22.
Programming the FPGA:Tools>Programmer • Check the Program/Configure box, then click Start. • Wait till the progress bar show 100% (done).