CCD-based Vertex Detector LCFI status report Nicolo de Groot RAL Conceptual design and goals

1. CCD-based Vertex Detector CCD-based Vertex Detector LCFI status report Nicolo de Groot RAL • Conceptual design and goals • Detector R&D program at LCFI • Development of Column Parallel CCDs • Readout chips for the CPCCD • Thin ladder program for mechanical support of the sensors • Summary

2. Conceptual Design and Goals 5 layers at radii 15, 26, 37, 48 and 60 mm; Low power, gas cooled; High precision, low mass support mechanics; Encased in light foam cryostat; Minimum external connections. Thin detector (< 0.1% X0) for low error from multiple scattering; Close to the interaction point for reduced extrapolation error; Readout time: 8 ms for NLC/JLC (read between trains) 50 μs for TESLA inner layer (read 20 times during the train); Pixel size  20 μm20 μm, stand-alone tracking, radiation hard, etc.

3. CCD Development Large area, high speed CCDs • Inner layer CCDs: 10013 mm2, 2500(V)650(H) pixels per CCD end; • Outer layers: 2 CCDs with size 12522 mm2 , 6250(V)1100(H) pixels; • 120 CCDs, 799106 pixels (20 μm square) in total; • For NLC/JLC: readout time  8 ms in principle sufficient, but not easy to achieve with standard CCDs, Column Parallel CCD is desirable; • For TESLA: • 50 μs readout time for inner layer CCDs : 50 Mpix/s from each CCD column • Outer layers: 250 μs readout, 25 MHz from each column • Column Parallel CCD is essential • Satisfy TESLA requirements, but thinking about NLC/JLC as well • CPCCD for JLC/NLC could be very advantageous

4. CCD Ladder End • Electronics only at the ends of the ladders; • Bump-bonded assembly between thinned CPCCD and readout chip; • Readout chip does all the data processing: • Amplifier and ADC per column • Correlated double sampling built-in • Hit cluster finding with threshold • Data sparsification, time stamping • Memory and I/O interface • CPCCD is driven with high frequency, low voltage clocks; • Low inductance layout for clock delivery.

5. CCD Development CPCCDs for TESLA: • Quality of 50 MHz clocks over the entire device (area = 13 cm2): • Power dissipation: • Large capacitive load (normally  2-3 nF/cm2), needs low clock amplitudes; • Low average power (  10 W) for the whole detector, but large peak power (TESLA duty cycle = 0.5%). • Feedthrough effects: • 2-phase drive with sine clocks – natural choice because of symmetry and low harmonics • Ground currents and capacitive feedthrough largely cancel CPCCDs for NLC/JLC: • Low readout frequency (780 kHz) – in principle few electrons noise could be achieved;

6. Our First CPCCD Manufactured by E2V Direct outputs and 2-stage source followers (SF) Two phase, 750(H)400(V) pixels, 20 μm square; Wire/bump bond connections to readout chip and external electronics; Two charge transport regions. 1-stage source followers and direct outputs on 20 μm pitch

7. First Signals First signals from one channel observed on 20 May 2003; Hits from 55Fe source clearly visible on the oscilloscope; Clocked with 1 MHz sine wave, full parallel readout; Particularly nice : small clock feedthrough. Great joy & happiness in the lab

8. CPC-1 Tests Clock drivers 3 pre-amplifiers Low inductance clock delivery, short tracks; Clock symmetry; Pulsed bias voltages to CPCCD; Shutdown mode – everything in a gas-cooled cryostat; On-chip temperature monitoring diode .

9. Stand-alone Performance 55Fe spectrum at 1 MHz readout Noise  60 electrons; Gain spread between channels  6%; CCD responsivity:  3.1 μV/electron. Single pixel hits spectrum using information from 3 adjacent columns

10. Stand-alone Performance Minimum clock amplitude  1.9 Vpp ! • Two main CPC-1 variants (by design) : • inter-gate barrier  1 V • inter-gate barrier  2 V • CPC-1 optimized for small signals; • Measured barrier : 1.9 V and 2.8 V; • Difficult to control small dose implants in E2V process; • Future plans: • Reduce clock voltage even further; • No implant, better barrier definition by geometry (dielectric thickness).

11. Stand-alone Performance Benefit of field enhanced implant  100 mV; CPC-1 clocked to 10 MHz with the same low clock amplitude of 1.9 V; 10 MHz is still low frequency for charge transfer; At > 10 MHz clock feedthrough rapidly increases. Clocking several nF of capacitance at high frequencies.

12. Clock Feedthrough On-chip clock delivery in CPC-1 not fully symmetrical by design – technological issues; Faster clocking will be attempted soon. P1 P2 P1 P2 buslines buslines

13. Plans In the next 2 months: Wire bond CPC-1 to CPR-1 : 1 in 3 channels, direct outputs and 1-stage SF; Bump bond CPC-1 to CPR-1, all channels (VTT Finland); Test both configurations; Study stand-alone performance at higher frequencies. After gaining enough confidence with CPC-1: Start design of CPC-2 : Much bigger chip : 8-10 cm in length (detector-scale); Better on-chip clock propagation; Test low clock operation in large area “stitched” CCD.

14. Readout Chip CPR-1 First bump-bondable readout chip (CPR-1) delivered Designed by the Microelectronics Group at RAL; Size : 6 mm 6.5 mm; Voltage amplifiers for the 1-stage SF outputs; Charge amplifiers for the direct outputs; 250 5-bit flash ADCs; Everything on 20 μm pitch; 0.25 μm CMOS process; Scalable and designed to work at 50 MHz. Wire/bump bond pads Voltage Amplifiers Charge Amplifiers 250 5-bit flash ADCs 250(W)132(L)5-bit FIFO Wire/bump bond pads

15. First Signals

16. Readout Chip CPC-2 CPR-1 is now under intensive tests Work on next generation chip (CPC-2) is near completion Features of CPC-2: Amplifier and ADC per column Correlated Double Sampling for low noise Kernel threshold 22 cluster finding (limited by 0.25 μm feature size) Data sparsification Time stamping Memory and I/O interface

17. Thin Ladder R&D A program to design CCD support structures with the following properties: • Very low mass (< 0.4% X0– SLD VXD3) • Shape repeatability to few microns when temperature cycled down to  –100 C; • Compatible with bump bonding; • Overall assembly sufficiently robust for safe handling with appropriate jigs; Three options: • Unsupported CCDs – thinned to  50 μm and held under tension • Semi-supported CCDs – thinned to  20 μm and attached to thin (and not rigid) support, held under tension; • Fully-supported CCDs – thinned to  20 μm and bonded to 3D rigid substrate (e.g. Be)

18. Semi-supported Option Beryllium substrate with adhesive pads Thinned CCD (  20 μm) CCD brought down Shims Adhesive Assembly after shim removal and curing 0.2mm Beryllium substrate (250 μm) 1 mm FEA simulations continuing: • Distortions of only few μm, optimise adhesive pitch and size; • Silicone adhesive: (e.g. NuSil), excellent at low temperature • Layer thickness  0.12% X0 XY stage for 2-dimensional profiling being assembled: • Laser displacement meter • Resolution 1 μm • Models made from steel + unprocessed Si were studied

19. A New Idea - Nanotechnology SLD had glue pads, which implies compression of silicon under cooldown. How to do better in 21st C? Micromechanical structure Maybe replace beryllium by some foam material – whatever gives best stiffness for least radiation length, regardless of thermal expansion properties

20. Summary • Detector R&D work at the LCFI collaboration: • Development of fast column parallel CCDs and their readout chips; • Precision mechanical support of thinned CCDs. • Most aspects of the R&D are applicable to all proposed LC machines; • High speed CPCCDs are mainly for TESLA, however NLC/JLC likely to benefit from slow CPCCDs. On track to achieve TESLA-compatible detector; • Speed requirements for NLC/JLC easily exceeded with CPCCD – focus on optimisation of noise, radiation hardness, etc. End result is likely to be an excellent detector; • Significant work still required, challenging combination of chip size and speed; • More results to follow in a couple of months. More information is available from the LCFI’s web page: http://hepwww.rl.ac.uk/lcfi