1 / 33

TAB & GAB Production Readiness Review

TAB & GAB Production Readiness Review. In a Nutshell We have the components, the boards, the money… Should we assemble the TABs and GABs? Concentrate on Hardware Design & Testing  Production Readiness Less Emphasis Project Justification, Algorithm Devel, Install/Commission.

oral
Download Presentation

TAB & GAB Production Readiness Review

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. TAB & GABProduction Readiness Review • In a Nutshell • We have the components, the boards, the money… • Should we assemble the TABs and GABs? • Concentrate on • Hardware Design & Testing  Production Readiness • Less Emphasis • Project Justification, Algorithm Devel, Install/Commission Hal Evans for the Nevis Group TAB/GAB PRR: 7-Oct-04

  2. The Nevis Team Students Chad Johnson, Jovan Mitrevski Postdocs Sabine Lammers, TBA Engineers Jaro Ban, Bill Sippach + Nevis Tech’s Faculty Hal Evans, John Parsons TAB/GAB PRR: 7-Oct-04

  3. The Tevatron Landscape Accelerator Plan: FY 05-09 2.8e32 ! install upgrades current peak L TAB/GAB PRR: 7-Oct-04

  4. Trigger Challenges Luminosity21032 BC396 ns L1 Limit~3 kHz TAB/GAB PRR: 7-Oct-04

  5. Detector Level 1 Level 2 Detector Level 1 Level 2 2.5 Mhz 3 khz CAL L1Cal L2Cal 2.5 Mhz 3 khz 1 khz CAL L1Cal L2Cal CalTrk c/f PS L1PS L2PS c/f PS L1PS L2PS CFT L1CTT L2CTT CFT L1CTT L2CTT SMT L2STT SMT L2STT L1Mu MU L2Mu L1Mu MU L2Mu FPD L1FPD FPD L1FPD Global L2 Lumi Framework Global L2 Lumi Framework Level 3 Level 3 Meeting the Challenge Run IIa Run IIb TAB/GAB PRR: 7-Oct-04

  6. Find EM LMs BuildEM Find EM+H LMs BuildJETs BuildTAUs Cal-Track Match: Arizona Et, Ex, Ey Sums TAB: Nevis Construct And/Or’s Filter + E  Et GAB: Nevis Digitize ADF: Saclay, MSU L1Cal Overview Cables: UIC TAB/GAB PRR: 7-Oct-04

  7. Board Rundown TAB/GAB PRR: 7-Oct-04

  8. Algorithm Flow Find Local Maxima Construct Objects Make Regions of Interest TT Input(corrected w/ ICR) Compare to Thresholds f h  LM Space TT Space ROI Space Jet Space TAB/GAB PRR: 7-Oct-04

  9. Objects Jet Algo EM Algo Tau Algo TAB/GAB PRR: 7-Oct-04

  10. Use ICR in Jets +Data to Cal-Track  All eta to each TAB Minimize Data Sharing  3 Identical outputs from each ADF (4x4x2 TTs) Each TAB: 40x9 inputs & 31x4 outputs Construct Local Maxima  SW Chip input 9x9  SW Chip output 4x4 TAB 7 =31-28 TAB 6 =27-24 TAB 5 =23-20 TAB 4 =19-16 TAB 3 =15-12 TAB 2 =11-8 TAB 1 =7-4 TAB 0 =3-0 10 10 10 =39-0=31-28 =39-0=27-24 =39-0=11-8 =39-0=23-20 =39-0=19-16 =39-0=15-12 =39-0=7-4 =39-0=3-0 ADFs79-70 ADFs69-60 ADFs59-50 ADFs49-40 ADFs39-30 ADFs29-20 ADFs19-10 ADFs9-0 Algo’s vs Architecture TAB/GAB PRR: 7-Oct-04

  11. VME/SCL Board • New Comp. of TAB/GAB system • proposed: Feb 03 • change control: Mar 03 • Interfaces to • VME (custom protocol) • not enough space on TAB for standard VME • D0 Trigger Timing (SCL) • (previously part of GAB) • Why Split off from GAB • simplifies system design & maintenance • allows speedy testing of prototype TAB • Fully Tested: Jun 03 local osc’s & f’out (standalone runs) VME interface SCL interface serial out x9(VME & SCL) DONE TAB/GAB PRR: 7-Oct-04

  12. TAB Channel LinkReceivers (x30) DC/DC conv power VME/SCL L2/L3 Output (optical) ADF Inputs (x30)thru custom b’plane Output to GAB Global Chip Output to Cal-Track (x3) Sliding WindowsChips (x10) TAB/GAB PRR: 7-Oct-04

  13. GAB power VME/SCL L2/L3 out to TFW TAB Inputs (x8) TAB/GAB PRR: 7-Oct-04

  14. Data-Eye View of L1Cal L2Cal& L3 L2Cal& L3 18016b ADF S.W. 9 ???16b Rcv 3 Global10 4912b+ 312b sp. And/Or x 10 x 8 x 30 x 80 S.W. 0 2112b+ 412b sp. Rcv 0 ADF 516b+ 216b sp. 516b+ 216b sp. 368b+ 68b sp. 516b+ 216b sp. 64b+ 16b sp. TAB GAB all data xmit & math operations donebit-serially @ 90 MHz CalTrk CalTrk TAB/GAB PRR: 7-Oct-04

  15. Intra-TAB: SWGlobal Clusters 12 lines 16-EM + 16-H+ 16-TAU each clust = 3-bits(highest of 7 thr’s pass) Sum(EM+H Et) 4 lines sum over  for each  Data for L2/L3 2 lines on L1 Accept Stat/BX/Frame 3 lines Spare 4 lines TAB to GAB: GlobalRcv EM Counts 12 words H Counts 12 words TAU Counts 12 words 6 thr’s – 2 bit counts S,C,N regions Sum(EM+H) 3 words Et, Ex, Ey Stat/Ctrl/… 7 words Spare 3 words TAB to GAB Data Path All Formats: www.nevis.columbia.edu/~evans/l1cal/hardware/tab/tab_gab_comm.html TAB/GAB PRR: 7-Oct-04

  16. Data Transmission TAB/GAB PRR: 7-Oct-04

  17. TAB/GAB Timeline No Layout Problems found with any of the Boards TAB/GAB PRR: 7-Oct-04

  18. TT inputs raw TTs SWalgos 0 Chan Link algo output VME access Internal TAB Testing TAB Simulation (Trigger Rate Tool) GAB data MC Events algo output Cal-Trk data raw TTs L2/L3 data (x-checked w/ tsim_l1cal2b) bit by bit comp bit by bit comp G-Link TT inputs raw TTs SWalgos 9 input mem L2/L3 data Chan Link GAB GlobalAlgos algo output Cal-Trk data GAB data Cal-Trk • all internal connections tested (tau only partially) • using compare’s to debug firmware & simulation TAB/GAB PRR: 7-Oct-04

  19. G-Link input mem L2/L3 data ECL Out GlobalChip input mem input mem TFW data Rcvr0 Rcvr3 input data from TAB from TAB rcvr output rcvr output Internal GAB Testing TFW data GAB data TAB Simulation (Trigger Rate Tool) MC Events algo output rcvr output Cal-Trk data raw TTs L2/L3 data L2/L3 data bit by bit comp • O(10??) events tested (rcvr  Global)  those lines tested • Global  ECL Xmit signals tested with ECL Test Card TAB/GAB PRR: 7-Oct-04

  20. SCL Timing & VME extensively exercised at Nevis and DØ used in ADFTAB tests ADF  TAB Channel Link Parameters probed w/ Test Card insensitive to: PLL range, deskew, DC balance, pre-emphasis At DØ w/ ADF error free (parity) xmit for >15 minutes working on bit-by-bit check Use of Channel Link provides clear spec ! TAB/GAB I/O TAB/GAB PRR: 7-Oct-04

  21. TAB  Cal-Track sync’ed TAB output w/ L1Muon board at DØ varied TAB output & saw corr. variation in L1Muon Trigger rate Latency: SW inp  SLDB in= ~630 ns TAB L2/L3 several events sent to L1Cal VRB under DØ timing TAB events to tape soon TAB  GAB LVDS transmission checked w/ Test Card safety margin of >400 ps >109 events TABGAB O(106) events 2 TABsGAB GAB  TFW Signal paths checked using ECL Test Card GAB  L2/L3 identical to TAB TAB/GAB I/O (cont) All Internal & External Hardware Paths Checked TAB/GAB PRR: 7-Oct-04

  22. Remaining Firmware TAB • Tau algorithm to be verified • Change to Atlas EM algo ? • Finalize L2 output • Finalize monitoring • Simulation of full TAB GAB • Only skeleton of Global chip firmware existsNeed to add • Trigger Terms • Monitoring • L2 output TAB/GAB PRR: 7-Oct-04

  23. What’s Next ? • If we’re given the Green Light – produce: • 10 TABs • 3 GABs • Testing at Fermilab • Have (nearly) enough hardware now for Nevis + DØ Tests • 2 VME/SCLs; 2 TABs; 1 GAB; 2 TAB/GAB crates • Can send out some new boards as they pass tests TAB/GAB PRR: 7-Oct-04

  24. Conclusions We believe that we’re ready to assemble • hardware has been checked • no changes from prototype • all components ordered (most arrived) + PCBs here • money is in hand (Hal’s CAREER grant) Risks of Going Forward • TAB: essentially none • GAB: some hardware paths not yet fully tested Risks of Delay • PCBs are aging (produced ~1 year ago) • Atlas efforts intensifying THANKS to the Committee for their Help ! TAB/GAB PRR: 7-Oct-04

  25. Extra Slides TAB/GAB PRR: 7-Oct-04

  26. HadIsolation X EMIsolation RoI / EM cluster Simple “1x2 or 2x1” Algorithm Serial Adders EM(0,0) “2x2” EM Algo LM Finder EM(0,1) EM(1,0) EM(1,1) Serial Adders Serial Comparators EM(0,0) LM Finder EM(0,1) EM(1,0) “1x2 or 2x1” EM Algo EM(0,0) • No extra latency • Chosen cluster still indexed by LL corner of 2x2 region TAB/GAB PRR: 7-Oct-04

  27. Data in the TAB TAB/GAB PRR: 7-Oct-04

  28. SW to Global Chip Data EM/Jet/Tau Results 12 words • for each algo &  = 2,3,4,5 send out 12-bit word encoding highest threshold (7-1 or 0=none) passed by each of the four ’s in that  Global Sums 4 words • for each  = 2,3,4,5 send out 12-bit word containing EM+HD over four ’s in that  Simulation Code for all this • tsim_l1cal2b relies on DØ software environ. • standalone being tested w/ hardware TAB/GAB PRR: 7-Oct-04

  29. TAB to GAB Data • EM/Jet/Tau Results 36 words • for each algo &  = 2,3,4,5 send out encoded 12-bit words for  = S,C,N containing 2-bit counts of no. of objects passing each of 6 thresholds • Global Sums 3 words TAB/GAB PRR: 7-Oct-04

  30. Data to Cal-Track Match Mask Definition: • Bit 07unused • Bits 06 – 00 set if threshold j is passed www.nevis.columbia.edu/~evans/l1cal/hardware/tab/tab_to_caltrack.html TAB/GAB PRR: 7-Oct-04

  31. Short Term Plans TAB/GAB PRR: 7-Oct-04

  32. Road to Installation (Jul 05) • Operations & Stability run test system • crashes/deadtime meas. in test syst. • reliable downloading use in test syst. • monitoring tools software in place • param determination software in place • unpacker/reco stable data from test syst • Trigger Quality data & MC • rates & efficiencies pred w/ MC – verify w/ data • trigger definitions (L1,L2,L3) in place well beforehand • filter coeff’s, thresholds, and/or terms, trigger list Note: all of these must be Documented TAB/GAB PRR: 7-Oct-04

  33. Testing Trigger Quality Splitters  Data Available before Installation • at most 16-EM + 16-H  cannot test Sliding Windows Possible Chain to Rate/Eff Estimates • Define Triggers • trig-list, and/or, thresh, filt. coeff’s • Using Splitter Data derive TT response • compare ADF Et(TT) output w/ Precision Readout correct MC modeling of Et(TT) • probe pathological cases using TWG • MC models TAB Algorithms • sliding windows algorithm is deterministic • use standalone MC to look for algorithm pathologies • MC models And/Or terms & Trigger List  Rates & Eff’s • need to test QCD MC vs. Data w/ Run IIa Trigger TAB/GAB PRR: 7-Oct-04

More Related