ECE 551 Digital System Design & Synthesis

1. ECE 551Digital System Design & Synthesis Lecture 12 “To synthesis, and beyond…”

2. So, the thing finally synthesized! • So, what have you created so far? • A list of the required hardware cells • A netlist describing their interconnections • A simulation model that hopefully reflects reality more accurately than the pure HDL-level simulation • Includes semi-accurate logic delays

3. Now What? • After synthesis, we have a netlist mapped to our specific tech library • ROMs • PLDs • FPGAs • Standard cells • Custom logic • Choose implementation platform based on cost and performance requirements

4. ROMs • Use like a GIANT truth table • Can be inefficient forsimple logic! • Gates • Specify just the 1’s • Specify just the 0’s • ROM • Has to specify both! • All outputs for all possible minterms address data a b c d x y z 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 0 0 1 0 0 0 1 1 0 1 0 1 0 1 0 0 1 0 0 1 1 0 0 1 1 1 0 1 1 1 0 0 0 0 1 1 1 0 0 1 0 1 0 . . . . . . . . . . . . . . . . . . . . . 1 1 0 0 0 1 0 1 1 0 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0

5. ROMs • Use like a GIANT truth table 0 0 0 0 a 0 1 1 0 1 1 0 1 0 0 0 1 1 x 1 b 0 1 0 0 1 0 address 0 1 1 1 data y 0 1 1 0 c 0 1 0 . . . . . . 1 z . . . 0 d 0 1 0 0 1 1 0 1 1 1 1 0

6. ROMs • Use like a GIANT truth table • 64K ROM: 8K entries x 8 bits (13 addr. lines) • 8 Boolean functions using any of these 13 1-bit variables a s b t c d u e f v g address data w h i x j k y l z m

7. ROMs • Use like a GIANT truth table • 64K ROM: 8K entries x 8 bits (13 addr. lines) • 2 4-bit functions of 3 4-bit variables (plus flag) • Other options possible a s b t c d u e f v g address data w h i x j k y l z m

8. ROM Logical Structure

9. ROM Circuit Structure

10. Erasable Programmable ROM (EPROM)

11. Flash Memory • A flash memory is an electrically erasable PROM configured with additional circuitry to allow erasure/programming blocks of memory (e.g. 16-64 Kbytes) in circuit. • Widely used as the program storage memory for computers and embedded systems, as well as data storage memory (audio, video, file systems) • High endurance 100k/1M+ erase cycles • Flash memory (SSDs) are cost-competitive with magnetic disks up to several GB, with no mechanical shock issues, and much better random-access times. • Some FPGAs use flash memory instead of SRAM to allow instant-on behavior and not expose IP.

12. Comparison of ROMs

13. ROMs • Cheap – couple bucks each • Reuse EEPROMs with different truth tables • Non-volatile - keep values when power gone • Very slow compared to gates (memory read) • Combinational-only • Limited to fairly simple designs (e.g., 20 or fewer inputs) due to exponential scaling • ROMs are good for complex operations that use few variables (trigonometry, matrix inversion, etc.) • They are often used in combination with other types of logic

14. PLDs • Programmable Logic Devices • PLA (Programmable Logic Array) – programmable AND and OR arrays • PAL (Programmable Array Logic) – programmable AND array and fixed OR array • Programming done at points where wires cross PAL PLA Inputs Inputs Outputs a !a a !a b !b c !c d !d b !b c !c d !d Outputs x Product Terms y x y

15. PLDs • Programming points where wires cross • x = a b c + a d • y = a b c d + a b d + b c d PAL PLA Inputs Inputs Outputs a !a a !a b !b c !c d !d b !b c !c d !d Outputs x Product Terms y x y

16. PLDs • Moderate per-unit price – 1s to 10s of $ • Most are re-programmable • Faster than ROMs • Relatively slow compared to gates • Programming points cause delay • Limited complexity • “Complex” PLDs have sequential ability, but are still too limited for very complex designs • Crossbar design scales poorly with number of inputs • Good when you don’t need the complexity of FPGA and want to save money.

17. FPGAs • Field Programmable Gate Array • Temporary (Flash/SRAM based) • Permanent (Anti-fuse) not as common • Pros • Allow for very complex implementations • Generally re-useable (upgrades/bug-fixes/prototype) • Low non-recurring engineering (NRE) costs • Cons • Expensive per-unit (10s-100s of $) • Slower than gates • Programming points • MPGA – mask-programmable (one time)

18. Programming an FPGA • Most designs based on SRAM • During configuration, the SRAM bits in the device are written with the desired values • Note that this means that your IP is being passed into the FPGA in a serial stream for the whole world to see! • Different circuits implemented based on values set in SRAM bits that form LUTs, control multiplexers, and make routing connections

19. Routing Elements • Programmable connection • Programmable bypass P Routing Resource #1 Routing Resource #2 OUT DFF SIGNAL P

20. Logic Elements • Look-Up Table (LUT) • Essentially a very small memory • Most common size is 4-input LUT P1 0 P2 1 P3 2 OUT P4 3 P5 4 P6 5 6 P7 7 P8 a b c

21. Logic Elements • Look-Up Table (LUT) Example • OUT = a XOR b XOR c 0 0 1 1 1 2 OUT 0 3 1 4 0 5 6 0 7 1 a b c

22. Logic Elements • Look-Up Table (LUT) Example • OUT = ab + ac + bc 1 0 0 1 1 2 OUT 1 3 1 4 1 5 6 0 7 1 a b c

23. Logic Elements • Look-Up Table (LUT) • Extremely flexible in implementing logic • Can implement any function! • Larger and slower than just using gates P1 0 P2 1 P3 2 OUT P4 3 P5 4 P6 5 6 P7 7 P8 a b c

24. FPGA Logic Structure • “Cell” or “logic block”: • 1 or more LUTs (generally 4-input) • At least one D flip-flop • Possibly fast carry logic • Connect several logic blocks to form circuit I1 I2 I3 I4 Cout Cin carry logic DFF 4-LUT OUT

25. Xilinx 4000 Combinational Logic Block

26. Xilinx 4000 FPGA (# of CLBs not to scale)

27. FPGA Summary • Allow for complex implementations • Generally reuseable (upgrades/bugfixes/prototype) • Low non-recurring engineering (NRE) costs • Relatively expensive per-unit (10s-100s of $) • Slower than pure gates (programming points), but FPGAs are normally first to latest technology • Newer FPGAs incorporate memories, multipliers, peripherals, and even processors all on the same chip

28. FPGA Trends • Hardware specialization • Memory block hierarchies • I/O interfaces • High-speed serial I/O • Clock management • Hardware for DSP (MAC units) • Intellectual Property (IP) cores • Hard-cores • Soft-cores • http://www.altera.com/products/ip/ipm-index.html • Conversion to mask-programmed devices • Altera Hard Copy, Xilinx Easy Path • Current Technology Examples...

29. Xilinx Virtex-5 • Xilinx’s nearly top of the line FPGA • 65nm process technology • 550MHz RAM blocks • 6-input LUTs • Serial connectivity • Ethernet MACs • Rocket I/O serial 3.25Gbps • PCI Express endpoint • Enhanced DSP blocks (25x18, 48b accum) • 1760 pin BGA with 1200 I/O • EasyPath

30. Xilinx Virtex-5 Applications

31. Xilinx Virtex-5 Family

32. Altera Stratix III

33. Stratix III

34. Stratix III

35. Altera Stratix III

36. Altera NIOS

37. Altera NIOS

38. Altera NIOS

39. Stratix III vs. Virtex-5 http://www.altera.com/literature/wp/wp-01007.pdf

40. Stratix III vs. Virtex-5

41. More Current Products • Actel FPGAs • Flash-based design eliminates configuration time • Less susceptible to radiation induced upsets • Also manufactured in antifuse technology

42. Mask-Programmable Gate Arrays • Mask-programmable (MPGAs) • Fixed logic elements, metal routing added Fixed Spacing Metal interconnect placed in channels between cells … Transistor / gate Base Cell

43. MPGAs • Cheap per-unit pricing ($1s-$10s) • Fast compared to ROMs/PLDs/FPGAs • Simpler Mask than Standard Cell (routing only) • Fixed gates available • High non-recurring engineering (NRE) cost - design time, mask fabrication... • $10K-$100Ks • Best for medium-to-large quantities • Used for medium-to-high-volume designs, or hardware that must be faster than FPGA

44. Gates and other small structures Can also use macroblocks Groups of pre-optimized cells Larger custom-layout structures Better logic density Standard Cells From: http://www.zuraleff.com/layout

45. Standard Cell Layouts Gate, flip-flop, 1-bit adder, … … Adjustable Spacing Metal interconnect placed in channels between cells Megacells

46. IC Layout Styles • Technologies in terms of layout styles: Standard Cell Gate, flip-flop, 1-bit adder, … Adjustable Spacing … Metal interconnect placed in channels between cells Megacells Gate Array Fixed Spacing Transistor / gate … Base Cell

47. Standard Cells • Cheap per-unit pricing ($1s-$10s) • Achieve better logic density than MPGA • Fast compared to ROMs/PLDs/FPGAs • High NREs (design time, mask fabrication...) • $100Ks-$10Ms • More expensive masks than Gate Arrays • Used for • Large quantities and/or • Performance-critical operations

48. Custom Logic • Manual layout • Extremely high NRE • Huge design time! • Even longer verification time • Maximum performance and density • PLD/FPGA physicalhardware is custom logic • They sell a LOT of them! • You don’t have to amortize all of their NRE, just part

49. Hardware Implementations • Making the right platform choice is one of the most important decisions for a design project’s success • There is no one “best” method • Tradeoffs between cost, speed, time-to-market, upgradeability, power efficiency • Technological changes are shifting traditional design choices. Engineers must be ready.

50. Hardware Trends • Standard Cell & Custom getting more expensive • Validation is getting harder with smaller gates and more complex designs, and is not scaling well w/Moore’s Law. • Licensing of IP is being used to counter-act NRE • “Hard” (layout) and “Soft” (HDL) IP cores • ARM architecture a great example