ACPD Presentation at SiliconWorks ( Automated Custom Physical Design)

1. ACPD Presentation at SiliconWorks(Automated Custom Physical Design) Cadence Korea May.13.2003 SY.Lee

2. Agenda • What is ACPD? • Virtuoso-XL • VCP • VCR • PDK • RoadMap

3. What is ACPD ?Automated Custom Physical Design • Complete automated full custom layout methodology for digital, analog and mixed technologies at all levels of the design hierarchy • No compromises: Layout results are equal to manual full custom • Low risk: Customer proven solution in use worldwide • Provides a measurable and consistent productivity increase of 4X - 10X on average compared to current methods ACPD Tools Methodology

4. Virtuoso® Schematic Composer CMOS Process Library with Pcells. Manual Physical Design Layout Methodology No connectivity Physical Handoff No constraints or automated routing Virtuoso® Layout Editor with Pcells Many DRC/LVS loops to fix errors Diva DRC,LVS Total time for Block Creation: typically 7 days Total time for Chip Assembly: typically 6 weeks

5. Virtuoso® Schematic Composer Netlist Process Design Kits (PDKs) Virtuoso® XL (VXL)andROD Pcells Virtuoso® Custom Placer (VCP) DIVA DRC/LVS ACPD Methodology Introduced in 1999 Connectivity Driven Layout Constraint and Connectivity Based Editing CMOS Process Library with Pcell’s. Automated Device Placement Virtuoso® Custom Router (VCR) /Cadence Chip Assembly Router (CCAR) Constraint Driven Correct-by- Construction Routing Number of DRC/LVS Errors Significantly Reduced Total time for Block Creation now -1 day Vs 7 DAYS (7X) Total time for Chip Assembly now -1 day Vs 6 WEEKS (30X)

6. = MONTHS Placement Generation Place Routing Verification Virtuoso® Schematic Composer • Virtuoso® XL Layout Editor • Custom Placement • Interactive Routing Connectivity & constraints Assura®/Diva (DRC/LVS) = DAYS Generation ACPD: METHODOLOGY AND PRODUCTS • Provides consistent 100% LVS & DRC correct results using Connectivity & Constraints • Generates faster more accurate devices using advanced interactive editing techniques • Reduces the layout timedramaticallywith automated placement and interactive routing • Maximizes custom layout productivity to deliver handcrafted quality in a fraction of the time

7. Virtuoso-XL Virtuoso®-XL Layout Editor is the next-generation, connectivity- and constraint-driven layout design environment. A task-oriented design approach provides direct access to automated placement, routing, verification and a robust set of interactive layout editing utilities. This new physical design solution maximizes custom layout productivity to deliver handcrafted quality layout in a fraction of the time of traditional methodologies • Provides a unified and consistent layout editing environment • Includes full-function polygon editing for high-performance, handcrafted IC layout • Automatically chains and folds transistors • Provides fast cell-level layout • Ensures increased productivity and correct-by-construction results • Provides fast device manipulation with stretchable parameterized cells (Pcells)

9. Rows displayed for preplacement DEVICE GENERATION Pins generated from template Pcells generated from netlist or schematic parameters

10. Alternate independent connectivity sources: schematic netlist Similar use modes and capabilities Imported netlists managed by DM Connectivity driven - Netlist-Driven Vsc VXL Edit, Place, Route... Netlist * SPICE … * M01 2 3 gnd 27 W=2 L=3 M02 3 5 g1 15 W=2u L=4u M03 4 5 g2 216 W=1u L=1u M04 5 6 g3 11 W=3u L=1.2u M05 5 6 g4 12 W=3u L=1u M12 3 5 g1 15 W=2u L=4u M13 4 5 g6 26 W=1u L=1u M14 5 6 g7 11 W=3u L=1.2u M15 5 6 g8 12 W=3u L=1u ...

11. A B A B (1) B is moved to overlap A (3) A and B are transformed and snap to min dist. A B (4) When A is moved away, reverse transformations occur to both instances Layout editing - Automatic Abutment • DRC correct • Constraint correct • Technology independent • Backward compatible • Customizable • Interactive • Post-processor after placement

12. Schematic reference CBE link Virtuoso XL Composer Edit Place Route ... (3) (1) (2) (1) Select unplaced component from schematic (3) Interactively place newly created object (2) Drag mouse pointer into layout window Connectivity driven - Pick from Schematic • Constraint-driven interactive placement • Multiple simultaneous selections • Pre-placement as in schematic

13. Interactive Chaining & Folding (cont’d)

14. Stretchable pCells

15. Virtuoso® custom placer (Vcp) - Overview Available in 4.4.6 3Q 2000 Automatic and interactive support in Virtuoso XL Constraint-driven (physical placement constraints) Row-based placement: Transistor Devices Custom and Std. Cells Blocks Area-based placement Mixed mode placement

16. Standard Cells Filler Cells PLACEMENT RESULTS

17. Filler Cells

18. WE • Show Timing/Length Rule Constraints: Displays length rule indicators as a path with a length rule is edited. • Meter displays a negative number in green color if within the length rule limits. A positive number in Red color shows up when the path being created is outside length limits. • Octagon shows the extent to which a path can be routed within the length rules.

19. Wire to Keepout Wire Shape Path Search Wire to Via Wire to Wire Wire to Pin Via to Pin Virtuoso® Custom Router • Original and most proven IC shape-based area routing technology in the industry • Provides connectivity- and constraint-driven interactive and automatic routing with online DRC/LVS checking • Comprehensive set of routing constraints with hierarchical rule precedence • Supports cross-probing and dynamic updating between schematic and layout • Automated interactive and automatic power routing • Automated interactive bus routing

21. PDK (b) User 1 PDK (a) TBL only VCD VCD Seat Virtuoso VXL Pool of Tools User 2 VXL VCR & Proute VCR/CCAR DIVA & Assura DIVA VCD Seat VCP Methodology User 3 Installation Internet Training Q1 2001 VCD Seat VCD Solution Point Tools ØØØØØØØØØØØØØØØØØØ VCD Solution ACPD Methodology 99 year or TBL User 1 Virtuoso User 2 Virtuoso User 3 VXL Introduced in 1999

22. What is a baseline foundry PDK? • For example CMOS logic • Composer logic symbol library • N & P mos, resistor and capacitor Pcells • Virtuoso XL/VCP/VCR Tech and display files • Assura/Diva DRC/LVS decks (download from foundry site) • Foundries • e.g. TSMC…., UMC… etc.. • Technologies • e.g. .18u, .25u…, Logic.., MS…., RF… etc.. • Tested with VCD methodology • Supported (maintenance available) • Price book orderable item

23. Virtuoso Schematic Composer Virtuoso XL Custom Placer Custom Router Simulation Models Spectre, Spectre RF Virtuoso XL Process data Per FAB / Process e.g. TSMC .18 CMOS (proprietary data) Verification Rule decks DIVA & Assura DRC/LVS PDK Tool Support Schematic Symbols Simulation Models Foundry Build PDK Technology File PDK Components Parameterized cells ( Pcells) Foundry Verification Decks

24. Cell-Based AMS/Custom Custom IC Design 3rd Party Tool SOC Encounter 3rd Party Tool 3rd Party Tool Cadence IC Design EnvironmentOpenAccess Industry-Standard open-source model Leverages industry knowledge on one standard 5.0 supports OpenAccess in Q1 03 Improved tool and flow interoperability Standards Accelerate Technology Development And Reduce Costs

25. LINUX OS SupportIC Solutions Custom IC solution available 1Q03 Provide Enterprise class solutions through partnerships with HP, IBM and RedHat Physical verification rollout 3Q02 through 3Q03 Many digital solutions available now - remainder 4Q02