Aravindh Anantaraman * , Kiran Seth † , Eric Rotenberg * , Frank Mueller ‡

1. Enforcing Safety of Real-Time Schedules on Contemporary Processors using a Virtual Simple Architecture (VISA) Aravindh Anantaraman*, Kiran Seth†, Eric Rotenberg*, Frank Mueller‡ Center for Embedded Systems Research (CESR) *Electrical & Computer Eng./ ‡ Computer Science North Carolina State University † Qualcomm. Inc RTSS–25

2. Complexity in Hard-Real-Time Systems • Worst-case execution time (WCET) crucial for schedulability analysis • Contemporary processors are extremely complex • Branch prediction, pipelining, out-of-order execution • Improve average case performance • WCET unknown • Complex processors not used in real-time systems RTSS–25

3. Simple Processor Complex Processor Virtual Simple Architecture (VISA) Task X WCET = 10 ms Task X WCET = 10 ms Task X WCET = ?? (unreliable) Virtual Simple Architecture: give illusion of simple processor • Novel non-literal approach to static timing analysis • Use simple processor as proxy for complex processor • Dynamically guarantee WCET RTSS–25

4. Simple Processor Complex Processor Worst-case equivalent systems actual exec. time = 8 ms actual exec. time = 3 ms 100% 100% dynamic slack dynamic slack processor utilization processor utilization worst case actual case actual case worst case Virtual Simple Architecture (VISA) Task X WCET = 10 ms Task X WCET = 10 ms Virtual Simple Architecture: give illusion of simple processor Exploit dynamic slack for power/energy savings, other functionality RTSS–25

5. Previous Approaches • Avoid complexity • VISA allows complex processors to be used • Disable complexity during hard-real-time tasks • VISA disables complexity only when problematic • Continue research in timing analysis • WCET of simple proxy improved RTSS–25

6. VISA Overview • Provides real-time guarantees for contemporary processors • Approach • Execute tasks optimistically on complex mode • Gauge interim progress • Safe back-up mode for anomalous scenarios RTSS–25

7. Dynamic branch predictor Dynamic branch predictor • Complex mode • dynamic branch prediction • superscalar • out-of-order execution • Simple mode • static branch prediction • scalar • in-order execution • Complex mode • dynamic branch prediction • superscalar • out-of-order execution • Simple mode • static branch prediction • scalar • in-order execution Dual-Mode VISA Processor Static prediction Static prediction RTSS–25

8. WCET preserved in spite of missed checkpoint VISA in Action simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk2 chk3 chk4 WCEC’ chk1 1 1 Successful speculation in complex mode (2) 2 2 Misspeculation in complex mode 3 3 4 4 $$$ cash back! headstart dynamic slack RTSS–25

9. Contributions • Minimize headstart overhead • Novel zero-overhead VISA approach – dynamic headstart accrual • Extend VISA to multi-tasking systems • Energy evaluation in multi-tasking systems RTSS–25

10. chk1 chk2 chk3 chk4 PEC1 PEC2 PEC3 WCEC3 WCEC4 headstart3 chk1 chk2 chk3 chk4 PEC1 WCEC1 WCEC2 WCEC3 WCEC4 headstart1 Headstart Assessment simple mode complex mode RTSS–25

11. Explicit Padding Approach • Pad task WCEC with max headstart amount • Give padded WCEC to schedulability analysis RTSS–25

12. Dynamic Headstart Accrual • Harness naturally occurring dynamic slack in simple mode as headstart •  switch to complex mode RTSS–25

13. accrued slack > max (headstart2,3,4) ? NO accrued slack > max (headstart3,4) ? YES Dynamic Headstart Accrual simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 WCEC chk4 chk3 Successful speculation in complex mode 1 Misspeculation in complex mode 2 (3) 3 3 4 4 dynamic slack • First simple mode, then complex mode • No explicit headstart padding RTSS–25

14. accrued slack > headstart4 ? YES accrued slack > max (headstart3,4) ? YES Dynamic Headstart Accrual simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 WCEC chk4 chk3 1 Flexible: fluidly switch between simple and complex 2 3 (3) 4 Re-enable speculation after missed checkpoint RTSS–25

15. Explicit Padding vs. Dynamic Headstart Accrual • Explicit padding +Guaranteed speculation • Inflated WCETs  Unschedulable task-sets • Dynamic headstart accrual +Schedulability unaffected +Flexible switching • Dependent on dynamic slack in simple mode RTSS–25

16. VISA in Multi-Tasking Systems • Gauging mechanism (watchdog counter) disrupted • Adapt for multi-tasking • Interruption  save watchdog counter • Resumption  restore watchdog counter RTSS–25

17. Easy Integration in Multi-Tasking Systems • System software components depend on WCET • EDF scheduler, DVS scheduler, etc. • VISA preserves WCET abstraction • We demonstrate VISA in a hard-real-time system with Look-Ahead EDF-DVS [Pillai&Shin’00] RTSS–25

18. Look-Ahead EDF-DVS in VISA Simple processor VISA (Explicit padding) VISA (Dynamic headstart accrual) RTSS–25

19. Experimental Methodology • Cycle-accurate microarchitecture simulator • Wattch power models to measure power/energy [Brooks01] • 6 C-lab real-time benchmarks RTSS–25

20. Energy Savings RTSS–25

21. Average Frequencies RTSS–25

22. High Utilization Task-sets • Worst-case utilization (unpadded WCETs) = 1.0 • Cannot use explicit padding  task-set unschedulable • Dynamic headstart accrual works! RTSS–25

23. Energy Savings (U = 1) RTSS–25

24. Coarse-grained vs. fine-grained sub-tasks Coarse-grained sub-tasks 1 2 3 4 1 2 3 4 5 6 7 8 Fine-grained sub-tasks RTSS–25

25. Fine-grained vs. coarse-grained sub-tasks RTSS–25

26. Summary • VISA enables use of complex processors in safe real-time systems • Headstart calculation • Novel zero-overhead VISA speculation technique • dynamic headstart accrual • VISA extended to multi-tasking systems • 19% – 58% energy savings with respect to explicitly-safe simple processor RTSS–25

27. Questions? RTSS–25