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Instructional Processor

Instructional Processor. STACK. BUS B. BUS C. BUS A. 12. PC. IR. A1. A2. 1. REGS. 2. 2. MUX. A. ALU. R. B. MUX. STATUS. NZ. MDR. 12. MAR. MEM. ALU Multiplexers. BUS A 15-5. 0's,A 10-9. 0's,A 10-5. 1's,A 10-9. 1's,A 10-5. BUS A 4-0. BUS B 15-5. 0's,B 10-9.

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Instructional Processor

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  1. Instructional Processor STACK BUS B BUS C BUS A 12 PC IR A1 A2 1 REGS 2 2 MUX A ALU R B MUX STATUS NZ MDR 12 MAR MEM

  2. ALU Multiplexers BUS A15-5 0's,A10-9 0's,A10-5 1's,A10-9 1's,A10-5 BUS A4-0 BUS B15-5 0's,B10-9 0's,B6-5 BUS B4-0 Branch 0 1 SRC or DST S 0 0 0 1 1 1 Sign (IR10) S S S 0 1 Address S 0 1 11 5 Extend S ALU B15-5 ALU B4-0 11 5 ALU A15-5 ALU A4-0 418_09

  3. Control Signals • BUS_A • BUS_B • REGS_Read1 • REGS_Read2 • Extend • Address • ALU_Op • MEM_Read • MEM_Write • Inc_PC • Load_PC • Push_PC • Pop_PC • Load_IR • REGS_Write • Load_STATUS • Load_MDR • Load_MAR • Clear 418_09

  4. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OP MD OFFSET IR Branch Instruction Format 418_09

  5. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OP SRC DST VALUE IR Data Instruction Format EA = Effective Address vv = Upper 2 bits of Value * = SRC only 418_09

  6. Data Instructions 418_09

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