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Design Constraint Analysis

Design Constraint Analysis. Team 6: AJ Hartnett David Eslinger Curt Schieler Ken Pesyna. FPGA Selection. Design Constraints Make design cheap Need multiple clocks (data in, compression) 12 bit parallel ADC and DAC, pins to communicate with uC, 10+ pins for FIFO SRAM

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Design Constraint Analysis

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  1. Design Constraint Analysis Team 6: AJ Hartnett David Eslinger Curt Schieler Ken Pesyna

  2. FPGA Selection • Design Constraints • Make design cheap • Need multiple clocks (data in, compression) • 12 bit parallel ADC and DAC, pins to communicate with uC, 10+ pins for FIFO SRAM • Plan to do linear predictive coding, and rice coding on FPGA for speed purposes • Ability to quickly become familiar with product • Rationale • Cost • Number of PLLs • I/O pins • Number of registers/gates • TA experience • Existence of development kits at Purdue

  3. Parts for considerations • Altera: Cyclone III • >80 I/O pins • >20k registers • 4 PLLs • Karl has recent experience • Dev kits • $40-70 • Xilinx: Spartan 3a • >80 I/O pins • Low number logic blocks • Mike has non-recent experience • Dev kits • $25-50

  4. Winner • Altera Cyclone III • EP3C25E144C8N • 82 I/O pins • ~ 25k Logic blocks • 144-EQFP • $39.50

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