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RAPID: A Rapid Prototyping Methodology for Embedded Systems

RAPID: A Rapid Prototyping Methodology for Embedded Systems. Huy Nguyen, Thomas Anderson, Stuart Chen, Ford Ennis, Michael Eskowitz, Andy Heckerling, Tanya Kortz, George Lambert , Larry Retherford, Michael Vai HPEC 2009 23 September 2009.

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RAPID: A Rapid Prototyping Methodology for Embedded Systems

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  1. RAPID:A Rapid Prototyping Methodology for Embedded Systems Huy Nguyen, Thomas Anderson, Stuart Chen, Ford Ennis, Michael Eskowitz, Andy Heckerling, Tanya Kortz, George Lambert , Larry Retherford, Michael Vai HPEC 2009 23 September 2009 This work is sponsored by the Department of the Air Force under Air Force contract FA8721-05-C-0002. Opinions, interpretations, conclusions and recommendations are those of the author and are not necessarily endorsed by the United States Government.

  2. RAPID - Rapid Advanced Processor In Development RAPID Tiles and IP Library Control IO Known Good Designs Capture Form Factor Selection Main features of RAPID: • Composable board design process • Custom processor composed of tiles extracted from known-good boards • Form factor highly flexible • Tiles accompanied with verified firmware / software for host computer interface • Container framework allowing co-design of boards and IPs • Portable FPGA Container Infrastructure with on-chip control infrastructure, off-chip memory access, and host computer interface • Surrogate board can be used while target board(s) are being designed or purchased Sig. Proc. Custom Composable Processor Board VME / VPX System Architecture MicroTCA Design COTS Boards FPGA Container Infrastructure

  3. Composable Board Design Flow Physical Design Reuse tool Extract circuit block of interest (Known Good Circuit) Known Good Boards Tile Re-use Library Hierarchical Composite “Known Good Tile” Board design time Verify RAPID Design Board Reduces time 50% to 66% as well as increases probability of first-spin success

  4. RAPID System Development RAPID Processor Packet Forming Timing signals Sample Timing Control ADC data Data path DIQ FIR ABF Packet Forming Processed data Analog data ADC Control* Control* • 6 months head start on surrogate system • Overlapping of FPGA and board design • Standardized control interface allows smooth porting to objective system • 2 months saved in system debug and integration • Incremental integration with local storage for data path source / sink ~12 months Initial capability Full capability ~13-14 months RAPID board design Development Timeline *A. Heckerling, T. Anderson, H. Nguyen, et.al., An Ethernet-Accessible Control Infrastructure For Rapid FPGA Development, HPEC 2008.

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