Download
1 / 8
80 likes | 224 Views
High Performance NextGeneration Memory Technology and Beyond. Dean Klein, Vice President of Market Development Micron Technology, Inc. Predicted. DDR2. DDR3. DDR. SDRAM. Data Transfer Rate Trends PC Main Memory. DRAM bandwidth requirements are doubling approximately every 3 years.
E N D
High Performance NextGeneration Memory Technology and Beyond Dean Klein, Vice President of Market Development Micron Technology, Inc.
Predicted DDR2 DDR3 DDR SDRAM Data Transfer Rate TrendsPC Main Memory DRAM bandwidth requirements are doubling approximately every 3 years
256Mb DDR2 Preferred Memory Solution for 512MB DualChannel Systems • Signal integrity limits bus loading at higher transfer rates. No longer able to put 4 DIMMs on one memory channel 5 1 2 M B D I M M 5 1 2M B D I MM 2 5 6 M B D I M M 2 5 6M B D I MM 2 5 6 M B D I M M 2 5 6M B D I MM Total 4.26 GB/s for DDR533 Total 8.52 GB/s for DDR533 Memory Controller Memory Controller 4.26 GB/s 4.26 GB/s 4.26 GB/s Dual channel provides 2X the bandwidth
GDDR3 • Graphics memory will lead I/O definition for desktop and server main memory • GDDR3 features • 8 Meg x 32 configuration • Up to 800 MHz (1600 Mb/s) • 1.8V VDD/VDDQ • Four internal banks • 4n prefetch • ODT • Calibrated output drive
Memory perPin Data Rate Trends Graphics 4000 GDDR4 3000 GDDR3 2000 Device Data Rate (Mb\s per Pin) PC DDR3 1000 DDR2 0 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 Year
DDR3 Signaling • DDR3 requirement is 800 MT/s-1600 MT/s • Migration can leverage from GDDR3 • GDDR3 is designed for operation at 1000 MT/s-1500 MT/s • DQs on GDDR3 are pointtopoint • DQs utilize VDDQ terminated push-pull drivers Typical 128bit Bus/Dual Load Graphics System
DDR3 PC Data Bus Module 1 Rank 1 Rank 2 Single DIMM in pointtopoint configuration Term Term RCVR RCVR System Controller • Ondie termination simulations with two loads at 1066 MT/s data rate • Improved signal integrity Reads Writes Signal Voltage (V) Signal Voltage (V) Time (nanoseconds) Time (nanoseconds)
DDR3 Server Data Bus Module 1 Module 2 Rank 1 Rank 2 Rank 1 Rank 2 Hubs added to DIMM drive DRAMs and allow multiple DIMMs per DQ Bus Term Term Term Term RCVR RCVR RCVR RCVR Data Buffer Data Buffer DRVR DRVR DRVR RCVR DRVR RCVR System Controller HighSpeed System Bus More DIMMs Reads Writes • On-die termination simulations with two loads at 1600 MT/s data rate Signal Voltage (V) Signal Voltage (V) Time (nanoseconds) Time (nanoseconds)
