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Research Activities in Power Electronics at UCF. Presentation at Princess Sumaya University for Technology. Florida Power Electronics Center Orlando, Florida USA batarseh@mail.ucf.edu. Outline of topics. About Florida Power Electronics Center Single-Stage PFC Converters
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Research Activities in Power Electronics at UCF Presentation at Princess Sumaya University for Technology Florida Power Electronics Center Orlando, Florida USA batarseh@mail.ucf.edu
Outline of topics • About Florida Power Electronics Center • Single-Stage PFC Converters • Low Voltage DC-DC converters • Inverters • Generalized Analysis of DC-DC • Converters
WELCOME TO FLORIDA Orlando Area
FloridaPower Electronics Center Dr.Issa Batarseh – Director Dr.Wenkai Wu – Asst Director Power Factor Correction (PFC) Circuits - NASA Soft-Switching DC-DC Converters - I-4 Florida Initiative Low voltage AC-DC and DC-DC Converters - NSF Dynamic Modeling and Control - NSF Electromagnetic Interference and Compatibility - NSF Inverter Application / Photovoltaic Cell – Industry & I-4 High Frequency AC DPS – NSF & I-4 Maximum Power Point Tracking System Smart Electronic Load
Multidisciplinary Research Group Topologies and Converter System Dr. Issa Batarseh Magnetics Dr. Thomas Wu Power Devices Dr.J J Liou Modeling and Control Dr.Zhihua Qu Packaging Dr.Louis Chow
FloridaPEC - Team Peter Kornetzky Shiguo Luo Joy Mazumdar Wenkai Wu Khalid Rustom Wei Gu Duy Bui Wei Hong Shailesh Anthony Jia Luo Songqrian Deng Christopher Iannello Abdelhalim M Alsharqawi JaberA.Abu Qahouq Jay Vaidya Shilba Reedy FloridaPEC.engr.ucf.edu
Power Conversion TV sets Medical equipment AC/DC converter power supply Telecommunication device, and other industrial equipment Computer ~ Converter AC Source DC Load
Definition of Power Factor For linear load: For nonlinear load :
Special Case --Distortion factor, where --Displacement factor
Typical Line Current Waveform Without PFC Line current is zero when vl(t) < vc(t). PF 0.67 THD >110%
PFC Approaches i) Passive PFC converter ii) Active two-stage PFC converter iii) Active single-stage PFC converter
Three Basic PFC Approaches Passive PFC converter Active two stage PFC converter Active single stage PFC converter
Special Family--Single-stage PFC AC/DC Converter PFC stage and DC/DC stage share the same switch Single Loop
Prior Art Advantage Simple Least component count Disadvantage Inherent Low efficiency High DC Bus Voltage Stress Turn off spike (a) Boost/flyback combination DCM+DCM (Redl, 1994) Advantage No turn off spike Low voltage rated capacitor Disadvantage Inherent Low efficiency High DC Bus Voltage Stress (b) Boost/forward combination DCM+DCM (Russian circuit, 1992)
Rough DC power 1 DC/DC cell eff. 2 Final DC output power 12 PFC cell eff. 1 Ac input Conventional Energy transfer concept
Direct transferpower (1-k)1 1-k DC/DC cell eff. 2 DC output power k12 +(1-k) 1 DC power k1 PFC cell eff. 1 Ac input k New energy transfer concept k12+(1-k) 1>12
New Concept • Flyboost PFC cell + Flyback DC/DC cell • Single active switch + single controller
Operation mode • Flyback mode: |Vin| < Vcs – n1 * Vo • Boost mode: |Vin| > Vcs – n1 * Vo
Simulation results Operation waveform in one line cycle Trace 1 Current through flyback winding Trace 2 Rectified input current Trace 3 DC/DC stage current
Experimental Results • Measured Power Factor vs. line voltage • Measured Efficiency vs. line voltage • Measured storage capacitor voltage (Vs) vs. line voltage • Line voltage and line current at line voltage=110V AC. Trace A: Line voltage (100V/div, 5ms/div); Trace B: Line current (measured after auxiliary line filter;1A/div; 5ms/div). The measured Power Factor is 99.4%
Special application Bi-Flyback Converter • Inegrate Bifred and Flyboost topologies • Two flyback transformers, single switch • Single DC bus capacitor
Waveforms Line Voltage Input voltage: 110V Output watts 150W Line Current Line Voltage Input voltage: 220V Output watts 150W Line Current
Efficiency and Power Factor 200KHz/28V@5.35A
Key Features • Higher efficiency due to soft switching operation of the main switch. • Low DC bus voltage make commercially available capacitor can be used as the energy storage part • Higher efficiency due to direct energy transfer in Flyback mode • Higher power density due to high frequency operation, which also benefit from soft switching
Powering Future Generation of Microprocessors and ICsLow-Voltage High-Current Fast-Transient On-Board Voltage Regulator Modules(VRMs)
The Main Power Supply Requirements(Challenges) • 1. High output current slew rate (> 50A/s). • 2. Low output voltage ripple and overshoot during transient (< 2% of the nominal output voltage). • 3. High efficiency • 4. High power density. • 5. High VRM input current slew rate (<0.1A/s). • 6. Packaging, thermal design, and EMC.
Current and Voltage Roadmap Year1999200020012002200320042005 Vmax 1.8 1.8 1.5 1.5 1.5 1.2 1.2 Vmin 1.5 1.5 1.2 1.2 1.2 0.9 0.9 W 90 100 115 130 140 150 160 Imin(A) 50 56 77 87 93 125 133 Imax(A) 60 67 96 108 117 167 178 Lately, there are news about even lower voltages and higher currents expectations in the future (APEC’2001, March 2001)
Why Voltage-Mode Hysteretic Control and Interleave Technique? Effective &simple to apply The Voltage-Mode Hysteretic Control Tracks the output voltage (ripple) and keeps it within the required limits. Near instantaneous response to load transients. No feedback loop compensation is needed. No limitations on the switches conduction time Circuit simplicity • The Interleave Technique • High frequency output voltage ripple with lower switching frequency • Ripple cancellation • Current division between the phases • Fast transient response which is limited by the feedback control loop +
Initial Experimental PrototypeWaveformsPreliminary Results Phase 1 Drive Signal Input Voltage =12V Output Voltage =1.5V Output Current =30A Switching Frequency/Phase =400KHz Output Ripple Frequency =800KHz Phase 2 Drive Signal Phase 1 Inductor Current Phase 2 Inductor Current Total Current Output Voltage
Initial Experimental Results Three-Phase VRM Control Two-Phase VRM Control Four-Phase VRM Control
Transient Cancellation Control Method for Future Generation of Microprocessors The idea of the transient cancellation control scheme is to create a deliberate undershoot before an expected overshoot and vice versa to cancel the expected large overshoot to keep the output voltage within the allowable output voltage deviation limit. Ideal Output-Voltage Waveforms at High-to-Low Load Transient without the Transient Cancellation Controller Ideal Output-Voltage Waveforms at High-to-Low Load Transient with the Transient Cancellation Controller
Future Look on VRMs and their Control Methods • To satisfy future strict powering requirements of microprocessors especially the tight allowable voltage deviation (20mV), may have to be one or more of the following: • 1) Proactive instead of reactive, i.e, to be able to take a response action before the load transients occur instead of after. • 2) Future VRM controllers may need to be able to ‘learn’ the load behavior and/or apply advanced response techniques to reduce the VRM output voltage overshoots/undershoots and to have fast transient response. • 3) Methods such as fuzzy logic and neural networks may be applied to make the VRM controller ‘smart’. • 4) Advanced Topology techniques that have naturally the voltage deviation reduction (cancellation)
Conventional DC-DC Converters(Hard-Switching) Boost Buck Buck-Boost Cuk Zeta Sepic
Switching-Cell Sharing All the Conventional DC-DC Converters shares the same switching-cell With different orientation of the cell in a specific converter The Conventional DC-DC Switching-Cell
Zero-Voltage-Switching Quasi-Resonant ZVS-QRC Switching-Cell ZVS-QRC Cell Basic Switching-Waveforms
Zero-Voltage-Transition PWM ZVT-PWM Switching-Cell ZCT-PWM Cell Basic Switching-Waveforms
ZVT-PWM Family ZVT-PWM Buck ZVT-PWM Boost ZCT-PWM Buck-Boost ZCT-PWM Cuk ZVT-PWM Zeta ZVT-PWM Sepic
The Generalized Transformation Table Single Generalized Transformation Table is complete and applies to all cells
Generalized Gain Equation Generalized gain ( ): By using the normalized parameters: