1 / 15

ELE22MIC Lecture 8

ELE22MIC Lecture 8. ASll Examples 16 Bit Counters Buffalo Jump Table Interrupt processing (IRQ/RTI) Stack Frame & Base Pointer Wired OR. AS11 Example (1) -16 bit counters. * 16 Bit counter problems loop_counter rmb 2 ; declare 2 bytes for 16 bit counter

palila
Download Presentation

ELE22MIC Lecture 8

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. ELE22MIC Lecture 8 • ASll Examples • 16 Bit Counters • Buffalo Jump Table • Interrupt processing (IRQ/RTI) • Stack Frame & Base Pointer • Wired OR

  2. AS11 Example (1)-16 bit counters * 16 Bit counter problems loop_counter rmb 2 ; declare 2 bytes for 16 bit counter ; then execute code as follows: dec_count: dec loop_counter ; only one byte is decremented !!! rts ; How can we fix this problem? ; One way is to use a 16 bit register as follows: dec_count: ldd #FFFF ; we can loop 65535 times std loop_counter lots_of_loops: jsr do_something ; do something pshy ; save the y index register value ldy loop_counter ; load value of loop_counter -> Y dey ; decrement y = decrement loop_counter sty loop_counter ; store value of y-> loop_counter puly ; recover saved y index register value bne loop_again ; if (loop_counter <> 0), loop again rts

  3. 68HC11 Parallel I/O & Control (1)

  4. AS11 Example (2) - Bit IO (1) * The 68HC11 has single Bit Set & Bit Clear instructions set or clear * individual bits at the selected memory location. * The instruction format is BSET/BCLR MemoryAddress Mask * A ‘1’ in the Mask indicates this bit should be Set/Cleared * A ‘0’ in the Mask indicates that the bit will not be changed. * I.e. BSET bitwise-ORs the Mask onto memory * BCLR bitwise-ANDs the inverse of the Mask onto memory * We can declare equates as follows to access them: Bit0 EQU %00000001 ; = 1 Bit1 EQU %00000010 ; = 2 Bit2 EQU %00000100 ; = 4 Bit3 EQU %00001000 ; = 8 Bit4 EQU %00010000 ; = $10 Bit5 EQU %00100000 ; = $20 Bit6 EQU %01000000 ; = $40 Bit7 EQU %10000000 ; = $80 AllBits EQU %11111111 ; = $FF LowNyyble EQU %00001111 ; = $0F HighNyyble EQU %11110000 ; = $F0 LoopMax EQU 100 IOREG EQU $1000 ; start address of Configuration Registers PORTB EQU 4

  5. AS11 Example (2) - Bit IO (2) FlashLeds: ; Connect LEDs to PortB LDAA LoopMax ; A = 100 = Our loop counter LDX #IOREG ; X = $1000 BCLR PORTB, X AllBits ; PortB = %00000000 LOOPAGAIN: BSET PORTB, X BIT0 ; PortB = %00000001 BSET PORTB, X BIT1 ; PortB = %00000011 BSET PORTB, X BIT2 ; PortB = %00000111 BSET PORTB, X BIT3 ; PortB = %00001111 BSET PORTB, X BIT4 ; PortB = %00011111 BSET PORTB, X BIT5 ; PortB = %00111111 BSET PORTB, X BIT6 ; PortB = %01111111 BSET PORTB, X BIT7 ; PortB = %11111111 jsr wait_a_bit BCLR PORTB, X LowNybble; PortB = %11110000 BCLR PORTB, X HighNybble; PortB = %00000000 jsr wait_a_bit BSET PORTB, X HighNybble; PortB = %11110000 BCLR PORTB, X HighNybble; PortB = %00000000 DECA BNE LOOPAGAIN ; loop 100 times RTS

  6. Wired OR - IRQ A Wired-NOR gate is formed by connecting open-collector device interrupt lines together. Normal gates would fight causing high current drain and possibly damage the gate.

  7. IRQ Processing (1) Any device requiring attention activates an interrupt service routine simply by asserting its interrupt output. The interrupt causes the CPU to : 1. Complete the current instruction - delay interrupt servicing until the current instruction completes (delay of from 1 (ABA) - 41 (IDIV) clock cycles) 2. Push all registers - PC, X, Y, AccA, AccB & CCR 3. Mask interrupts by setting the I bit in CCR 3. Fetch the interrupt vector 4. Jump to the address fetched from the int. vector

  8. IRQ Processing (2) The Interrupt Service Routine (ISR) must then poll all devices connected to the IRQ pin and ask each device in turn: “Did you interrupt me?” Upon finding a device requiring service, perform the appropriate Input/Output/Processing and reset the device’s interrupt request (so that upon return the cpu is not immediately interrupted again). Upon successful servicing, the ISR must exit without altering the previously running program’s state. The ISR does this simply by executing the RTI instruction (ReTurn from Interrupt).

  9. IRQ Processing (3) The RTI instruction :Pulls all the previously saved registers from the stack, in the reverse order that they were pushed, so that all registers contain the previous values. Pul : CCR, AccB, AccA, Y, X, PC The last pul - Pul PC - Pulls (pops) the program counter which effectively transfers program execution to the instruction immediately following the instruction completed before the interrupt request was accepted. Pulling the CCR re-enables the CPUs ability to be interrupted as the I flag which was cleared will be cleared again.

  10. IRQ Processing (4) If the interrupt mask bit, I, in the CCR is unmasked during the ISR, then the IRQ line could cause one or more nested interrupts. This ISR nesting procedure would normally only be performed to provide more rapid response to a higher priority device.

  11. Stack Frame (1) In the C language, the function parameters are normally pushed in the reverse order that they are listed. This is to facilitate C’s format statements for example: Printf (“P1=%3d, P2=%4d\n”, P1, P2); would compile to: Push P2 Push P1 Push FormatStatement JSR Printf ; Printf knows where the ; format statement will be Add SP, #6 ; drop the parameters

  12. Stack Frame (2) The subroutine Printf expects to find the format statement as the first parameter on the stack. It then parses the statement, and determines how many more, and what type of, parameters are required. The return address is also placed on the stack. Also Local variables are pushed onto the stack. During the function these variables can be accessed on the stack frame as follows:

  13. Frame/Base Pointer (2) For the duration of the function execution a frame pointer can be set up using the X or Y registers, and the variables may be accessed using indexed addressing P2 EQU A P1 EQU 8 FormatStt EQU 6 LocalVar1 EQU 2 LocalVar2 EQU 0 TSX ; X = SP+1 (Setup Frame Ptr) LDD P1, X ; D = P1 (Fetch P1) STD LocalVar1, X ; LocalVar = AccD = P1

  14. Buffalo Routines Jump Table (1) ORG ROMBS+$1F7C .WARMST JMP MAIN warm start .BPCLR JMP BPCLR clear breakpoint table .RPRINT JMP RPRINT display user registers .HEXBIN JMP HEXBIN convert ascii hex char to binary .BUFFAR JMP BUFFARG build hex argument from buffer .TERMAR JMP TERMARG read hex argument from terminal .CHGBYT JMP CHGBYT modify memory at address in x .READBU JMP READBUFF read character from buffer .INCBUF JMP INCBUFF increment buffer pointer .DECBUF JMP DECBUFF decrement buffer pointer .WSKIP JMP WSKIP find non-whitespace char in buffer .CHKABR JMP CHKABRT check for abort from terminal

  15. Buffalo Routines Jump Table (2) ORG ROMBS+$1FA0 .UPCASE JMP UPCASE convert to upper case .WCHEK JMP WCHEK check for white space .DCHEK JMP DCHEK check for delimeter .INIT JMP INIT initialize i/o device .INPUT JMP INPUT low level input routine .OUTPUT JMP OUTPUT low level output routine .OUTLHL JMP OUTLHLF display top 4 bits as hex digit .OUTRHL JMP OUTRHLF display bottom 4 bits as hex digit .OUTA JMP OUTA output ascii character in A .OUT1BY JMP OUT1BYT display the hex value of byte at X .OUT1BS JMP OUT1BSP out1byt followed by space .OUT2BS JMP OUT2BSP display 2 hex bytes at x and a space .OUTCRL JMP OUTCRLF carriage return, line feed to terminal .OUTSTR JMP OUTSTRG display string at X (term with $04) .OUTST0 JMP OUTSTRG0 outstrg with no initial carr ret .INCHAR JMP INCHAR wait for and input a char from term .VECINT JMP VECINIT initialize RAM vector table

More Related