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Formal Techniques for Verification Using SystemC

Formal Techniques for Verification Using SystemC. By Nasir Mahmood. Introduction. The increasing complexity of designs, pushing designers to higher and higher levels of abstractions .

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Formal Techniques for Verification Using SystemC

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  1. Formal Techniques for Verification Using SystemC By Nasir Mahmood

  2. Introduction • The increasing complexity of designs, pushing designers to higher and higher levels of abstractions. • The major goal of SystemC is to enable verification at higher level of abstraction, enabling early exploration of system-level designs • The focus so far has been on traditional dynamic validation techniques

  3. Motivation • A micro-architecture is usually specified by a natural- language document, referred to as the micro-architectural specification document (MAS) • The micro-architecture is an extremely sophisticated algorithmic model. Validating it is bound to be hard. Implementing it and validating it directly in RTL is bound to be exceptionally hard, slow and expensive • The right level to develop a ‘golden specification model’ is at the algorithmic/functional/transaction level • The motto should change from “design first, then verify” to “specify first, then design and verify’

  4. Motivation Contd.. • Formal methods ought to be an important component in the verification of micro-architecture • There is a need for development of formal techniques • Formal property verification • Formal equivalence verification • Automated test generation • There is a need of verification at the right level of abstraction • Many of the assumptions/assertions written for higher abstraction could be translated into lower level of abstraction, thus reuse of test stimulus.

  5. Formal Techniques for SystemC Models • Dynamic validation is used test out the systemc models, and mostly simulation is run to verify • SystemC verification standard provides API for transaction-level verification, constrained and weighted randomization, exception handling and other verification tasks • So there is research challenge to develop formal techniques that augment standard SystemC verification

  6. Formal Techniques • Assertion-based validation • Explicit-state model checking • Symbolic Simulation • Symbolic model checking • Equivalence verification

  7. Assertion-based validation • Write properties of a formal language • Property Specification Language (PSL) or System Verilog Assertions (SVA • The simulation engine then monitors these properties during the simulation • Extending assertion-based verification to SystemC would mean that the same assertions can be used in a SystemC environment and in a RTL

  8. Explicit-state model checking • It exercises the design exhaustively – by keeping track of all nondeterministic choices (e.g., input values), we ensure that all of them get exercises • There is also a need to monitor the program states visited, to ensure termination of the search process • The real limitation of explicit-state model checking is the state explosion problem. To deal with large state spaces we need to introduce abstraction technique, but automating such techniques generally requires the use of symbolic model checking (BDD or SAT-based) to Testing and Runtime Verification

  9. Symbolic Simulation • The program is executed in an abstract setting, using symbols, rather than concrete values for variable. Each symbolic simulation path represents a whole class of possible program executions • By heaving a symbolic representation of this class of executions, we can reason about it symbolically, generate test cases and more • Similar work is done in Java and can be with SystemC

  10. Symbolic model checking • Symbolic model checking goes a step further in verifying temporal properties of designs • Instead of searching the state space explicitly, it is represented and searched by means of symbolic reasoning • we have formal semantics that describes the transition relation of the design. This is quite nontrivial for SystemC due to the heavy use of ob ject oriented machinery and the fairly involved simulation semantics • Similar work on Java may be extended to SystemC

  11. Equivalence verification • To formal verify the equivalence of SystemC models and RTL models, analogously to current technology for formally establishing equivalence of RTL models with Netlistmodels • This is a significant research challenge • Compatibility can be established between systemC and RTL model require that such events can also be monitored at RTL level

  12. Reference • Formal Techniques for SystemC Verification by Moshe Y. Vardi of Rice univeristy

  13. Questions/Comments?

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