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Debug Suggestions

Learn valuable tips like capturing a buffer of sample data, using fixed test patterns, and analyzing raw samples to identify bugs in FPGA testing. Discover how to address setup/hold errors and bit ordering issues effectively.

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Debug Suggestions

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  1. Debug Suggestions • Have a way to capture and output a buffer of sample data • Either using FPGA debug tools or output sample data to a test header and capture using a logic analyzer • Many ADCs have known fixed test pattern outputs • Toggle, arithmetic count, custom fixed pattern • If no pattern available, input *very* slow sine wave • Can get a ‘slow’ sine wave by sampling an IF that is very near sampling frequency • Example, if 100MHz sample rate, set IF to 100.01MHz for 10KHz sine • Logic analyzer view of raw samples can reveal many bugs • Misplaced bit order • Timing errors • Improper deserialization boundary

  2. Debug tips – Arithmetic count pattern Arithmetic count pattern (ramp) can quickly identify that bits are in the right position

  3. Debug Tips – Slow input sine wave If Ramp is not available, very slow sine wave may work almost as well Or, use custom pattern to walk a single ‘1’ through all possible bit positions

  4. Debug Tips – setup/hold errors Setup/hold errors (sometimes called sparkle) show as deviations from expected

  5. Debug Tips – bit ordering, pipelining Actual example of a timing bug – note bit 9 is seen one cycle early using ramp pattern

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