1 / 16

ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices

ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices. Decoders. Previous…. Programmable Logic Devices PLAs PALs. Decoder. Multiple-input/multiple-output device. Inputs ( n ) are less than outputs ( m ). Converts input code words into output code words.

panthea-zurlo
Download Presentation

ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. ECE 3110: Introduction to Digital SystemsChapter 6Combinational Logic Design Practices Decoders

  2. Previous… • Programmable Logic Devices • PLAs • PALs

  3. Decoder • Multiple-input/multiple-output device. • Inputs ( n ) are less than outputs ( m ). • Converts input code words into output code words. • One-to-One mapping :- Each input code produces only one output code. • Input codes :- Binary Code- Your Code ! • Output Codes 1-out-of-m code Gray Code BCD Code enable inputs

  4. Note “x” (don’t care) notation. Binary Decoder • n-to-2^n decoder : n inputs and 2^n outputs. • Input code : n bit Binary Code. • Output code : 1-out-of-2^n , One output is asserted for each input code. • Example : n=2, 2-to-4 decoder

  5. Binary 2-to-4 decoder

  6. MSI 2-to-4 decoder • Input buffering (less load) • NAND gates (faster)

  7. 74x139 : Logic Symbol -Truth Table • Active Low Enable, Active Low outputs • Truth Table Logic Symbol Inputs OutputsG_L B A Y3 Y2 Y1 Y0 1 x x 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1/2 74x139 Y0 Y0_L G_L G Y1 Y1_L A A Y2 Y2_L B B Y3 Y3_L

  8. Complete 74x139 Decoder

  9. 3-to-8 decoder

  10. 74x138 3-to-8-decoder symbol

  11. Decoder cascading 4-to-16 decoder

  12. More cascading 5-to-32 decoder

  13. Implementing the Canonical Sum • The binary decoder generates all minterms of n-variable logic function. • The canonical sum ( sum of minterms ) of a logic functions is obtained by adding all minterms of that function: -Match the order of input bits -Activate Enable inputs • Example : +5V 74x138 Y0 G1 Y1 G2A Y2 G2B F Y3 Y4 Z A Y5 Y B Y6 X C Y7

  14. Logic design using Decoders • Advantages : - Flexibility- Multiple-output Logic functions • Disadvantages :- Complexity : for large number of inputs ( 5-variable Function with 3 minterms ! F= AB’CD’E + A’BC’DE+A’BCDE’ ) • A practical alternative : PLD’s

  15. Decoder applications • Microprocessor memory systems • selecting different banks of memory • Microprocessor input/output systems • selecting different devices • Microprocessor instruction decoding • enabling different functional units • Memory chips • enabling different rows of memory depending on address • Lots of other applications

  16. Next… • Encoders • Reading Wakerly CH-6.5

More Related