Section 1: Overview of RATC Algorithms

1. Section 1: Overview of RATC Algorithms

2. RATC Algorithm Inputs • Look-ahead market models • Static input datasets of network model, generator bids, load, and renewable forecasts • Corrective control actions • State estimation • Network availability via topology processor • Generator availability • Load

3. Current Technology Solution Times • Day-ahead • 2 hours • Hour-ahead • 15 minutes • 15-minute ahead • 5 minutes • 5-minute re-dispatch • 2-3 minutes • Corrective control • <3 minutes

4. RATC Limitations and Triggers • RATC Limitations • Computational time (optimization and stability) • Triggers (additional details with Architecture presentation) • Operator • Line overload • Voltage violation • Frequency violation • Load shedding • Market-based

5. RATC Limitations and Triggers • RATC Limitations • Computational time (optimization and stability) • Triggers (additional details with Architecture presentation) • Operator • Line overload • Voltage violation • Frequency violation • Load shedding • Market-based

6. Evaluation Criteria • Primary criteria: • Objective, solution time, optimality gap, reliability improvements (feasible contingency set), renewable penetration, load served • Quantifiable thresholds • Current technology produces optimality gaps (does not guarantee solution is global) • Key goal of RATC: outperform global optimal solution with current technology • Even if RATC has an optimality gap, we plan to demonstrate that the RATC solution beats the global solution without RATC (current technology) • Local vs. global optimal solutions • Global optimality is not a priority • Local optimality is not a priority • Quality of proposed heuristics will be based on solution quality, optimality gap, solution time

7. Section 2: Progress Update

8. Algorithm Team Assignments

9. Greedy Algorithm To date: • Initial model development (sensitivity analysis) complete • Initial testing of cascading events (small scale test cases) By Dec. 2012: • Finalize model development • Parallelization of greedy algorithm & collaborate with LLNL (partial) • Scenarios: renewables, N-1 events, market based • RATC performance with breaker failure, AC infeasibility, instability, topology processor error (partial) • AC feasibility and stability check

10. MIP Heuristic To date: • Generic model development in pyomocomplete • Currently testing it on IEEE test cases • Min-Load-Shed variant tested for all N-1 and N-2 events • Evaluated effect on different load levels and ramp scheme By Dec. 2012: • Parallelizing heuristic in coordination with LLNL (partial) • Testing N-m events (10,000+ bus instances: TVA and PJM) • Scenarios: N-1, N-m, renewables, market-based (partial) • AC feasibility and stability check • RATC performance with breaker failure, AC infeasibility, instability, topology processor error (partial)

11. AC Feasibility To date: • Examination of alternative approximations of the AC OPF problem (and then modified for transmission switching) • Results show: consistency in switched line from the linearized AC formulation compared to non-linear AC formulation for some test cases and inconsistent results for other test cases By Dec. 2012: • Testing of AC feasibility for the greedy algorithm and MIP heuristic results

12. Voltage and Transient Stability Past: Data preparation and scenario investigation To date: • Scenarios to show the benefits of line switching for system stability are created on small systems: • AC flow validation (feasibility of steady state) • Dynamic simulation for switching lines, which includes excitation and voltage regulation controls, governor dynamics, and plant dynamics (line switching and dynamic response) • Stability margin validation through fault circuit analysis (large disturbances) • Results show that switching lines can relieve overflows, improve stability margin, reduce loop flow/wheeling effects, and reduce system loss

13. Stability Validation-continued • Validation process is clarified through the scenarios • Dynamic models for IEEE test systems are created based on data exchanges with TVA By Dec. 2012: • Stability testing for the greedy algorithm and MIP heuristic results for IEEE test systems

14. High Performance Computing To date: • Prior transmission switching model in AMPL has been converted into JAVA • Model has been loaded onto LLNL’s Hyperion supercomputing facility • Initial work on the PJM 15,000 bus model By Dec. 2012: • Initial parallelization of MIP heuristic and greedy algorithm

15. Section 3: RATC Algorithm: Greedy Algorithm

16. Greedy Algorithm Process • Greedy algorithm is a fast, real-time heuristic Collect system data Perform Sensitivity Analysis Simulate Line i for switching action + AC, Stability Check No Implement System improvement? No Yes Problem Solved? Stop Yes

17. Model Development Primary component of Greedy algorithm: • Sensitivity Study • Ranks lines from highest to least likely to provide improvement • Based on a dual variable • Dual variable: reflects marginal improvement by changing line’s setting • While this is a sensitivity study, mathematical structure of topology control suggests correlation between marginal improvement and actual improvement after switching the line

18. Generic DCOPF Formulation Objective: Min s.t.: [λ] ≤ ≤ , [] , [] , [] , []

19. Inclusion of Transmission Switching Objective: Min s.t.: (additional optimal power flow constraints) , [] , [] , [] , [] [] []

20. Sensitivity Analysis • The basic DCOPF formulation is made equivalent to the modified formulation by the constraints: [] [] • By applying KKT conditions, one can derive a relationship for the dual variables: • )

21. Ranking Procedure • [] – lines ranked from lowest value to highest • [] – lines ranked from highest value to lowest • [, ] – ranked from the lowest to highest values

22. RATC Procedure Potential switching action? Operator Trigger No Network topology processor Yes No AC feasibility check Candidate lines for switching Yes No Stability check State estimator: Load flow, Voltages, generator information Yes RATC greedy algorithm Implement Traditional contingency response

23. Results • RATC algorithm is developed to regain lost load caused by N-m events (malicious attacks, cascading failure) • Scenario: • 20 lines out of service • 5 lines have faults (determined by topology processor) • Determine switching sequence of out of service lines without faults • Initial tests completed

24. Section 4: RATC Algorithm: MIP Heuristics

25. MIP Heuristic • Topology optimization • Combinatorial problem • K Transmission lines, 2^K binary solutions • 2 variations (based on objective): • Minimize Generation Cost • Minimize Load Shed (Max Recovered Shed-Demand) where shed-demand is that which cannot be satisfied at the time of a contingency event

26. MIP Heuristic Procedure Identify objective type Determine best single line to switch Collect system data Stop No Improvement? Implement Next Iteration Yes Yes No New Config. AC Feasible/ Stable ? Solution time exhausted ? Stop Yes No Note: red process is a future inclusion into the heuristic

27. DCOPF Formulation with Transmission Switching (Min Gen. Cost) Objective: Min s.t.: (additional optimal power flow constraints)

28. DCOPF Formulation with Transmission Switching (Min Load Shed) Objective: Min s.t.: (additional optimal power flow constraints) Blue arrows indicate modifications from Min. Gen. Cost model : Unmet load at bus

29. MIP Heuristic - Min Load Shed • RSD := Recovered Shed-Demand. • Load shed at T=0 := load that cannot be met by an adjustment of line flows (no re-dispatch) at time of contingency • Unconstrained Dispatch RSD Solution := RSD obtained through line flow adjustment and unlimited-ramp re-dispatch (less than or equal to load shed at T=0) • Nontrivial case:= Contingency for which the unconstrained dispatch RSD solution is strictly less than the load shed at T=0 (i.e. have load shed after re-dispatch)

30. Realistic Scheme for MIP Heuristic - Min Load Shed

31. MIP Heuristic Results – NontrivialMin. Load Shed (cont) • IEEE-73 did not provide nontrivial cases • Single and double line failure did not provide nontrivial cases (will try greater #) Opt* - value obtained within a 1hr time limit with unlimited line switches/re-dispatch

32. MIP Heuristic Results - NontrivialMin. Load Shed (cont)

33. Section 5: Progress on First Year Go-No-Go Milestones

34. Go-No-Go: Algorithms • Algorithm development concluding • Initial small-scale IEEE test started • Results beating CPLEX 12 thus far • Feasibility in DCOPF demonstrated • Parallelization techniques started • Going forward: • To be confirmed: solution times, optimality gaps, benefits • AC feasibility check • Voltage and transient stability check

35. Appendix

36. Section 1: Extension: Overview of RATC Algorithms

37. RATC Process

38. Section 3: Extension: Greedy Algorithm

39. RATC Greedy Algorithm • Topology processor: identify candidate switchable lines and lines unavailable for switching • Input system operating condition (state estimation) and generator availability • Perform sensitivity analysis, create priority list, propose switching action • Check AC feasibility and stability • Implement

40. Overview on Current Status • Generic model development of the greedy algorithm complete • Currently testing it on IEEE test cases • Application: real time corrective control for: • Cascading outage/ malicious attack/ N-m scenario

41. Future Work: Greedy Algorithm • AC power flow validation and stability validation • Test the algorithm with other scenarios: • Variation of renewable resources • N-1 events • Market based studies • Failure of circuit breakers • Topology processor error

42. Section 4: Extension: MIP Heuristic

43. RATC MIP Heuristic (Min Gen Cost) • Topology processor: identify candidate switchable lines and lines unavailable for switching • Input system operating condition (state estimation) and generator availability • Propose switching action based on potential cost savings • Check AC feasibility and stability • Implement Note: red bullets are future inclusions into the heuristic

44. Past MIP Heuristic Results -Min. Gen Cost • Topology control applied to 5000-bus system of ISO-New England (and surrounding regions) • Without MIP Heuristic: • 84 Hour solution time produced less savings than the 3rd iteration of the MIP heuristic

45. Past MIP Heuristic Results – Min. Gen Cost (cont) • MIP Heuristic found 20 potential switching solutions for 12% cost reduction in 6 hours • Additional benefit: MIP Heuristic can be easily parallelized • Estimate solution time reduced to 15 minutes for 20th iteration with parallelization

46. MIP Heuristic To date: • DC model development complete • Initial testing of N-m events (small scale test cases) By Dec. 2012: • Scenarios: N-1, N-m, renewables, market-based (partial) • RATC performance with breaker failure, AC infeasibility, instability, topology processor error (partial)

47. Ongoing Tasks • Parallelizing heuristic in coordination with LLNL • Modeling other contingencies based on critical/ vulnerable assets • Testing min-load-shed variant on 10,000+ bus instances (TVA and PJM)

48. Concluded tasks • Generic model development in pyomo of the MIP heuristic complete • Currently testing it on IEEE test cases • Min-Load-Shed variant tested for all N-1 and N-2 events. • Evaluated effect on different load levels and ramp scheme (no ramping data for iee118_2)

49. Future Work • Inclusion of AC power flow validation and stability validation into heuristics • Test the heuristic with other scenarios: • Variation of renewable resources • N-m events, where m>2 • Increased load levels • Developing a new data-mining model to learn/predict the characteristics of switch-prone lines