Hassan Mostafa & M. Anis & M. Elmasry University of Waterloo, Ontario, Canada

1. Comparative Analysis of Power Yield Improvement Under Process Variations of Sub-Threshold Flip-Flops Hassan Mostafa & M. Anis & M. Elmasry University of Waterloo, Ontario, Canada

2. Outline • Introduction and Background • Motivation and Objectives • Simulation Procedure • Results and Discussions • Conclusion Introduction and Background

3. Outline • Introduction and Background • Variability • Classification and Design Methodologies • Sources • Variability and Yield • Variability and Sub-threshold logic • Motivation and Objectives • Simulation Procedure • Results and Discussions • Conclusion Introduction and Background

4. Variability Classification • Die-to-Die (D2D) • Affects all devices on the chip in the same way • e.g., all devices on a chip have the same Vt • Within-Die (WID) • Variations within a single chip • Affecting devices on the same chip differently • e.g., devices on the same chip have different Vt D2D WID Die index Introduction and Background

5. Performance Distribution Design Methodology Cost (e.g. power) FAIL Nominal 50% Timing Yield FAIL Corner-Based 100% Timing Yield FAIL Statistical >99.9% Timing Yield Design Methodologies (Overhead) Frequency www.nowpublishers.com Introduction and Background

6. Process Variations Sources [1] • Random Dopant Fluctuations (RDF) • As CMOS devices are scaled, number of dopant atoms decreases • The number of dopant atoms has variations around its nominal value resulting in Vtvariations • σVtα (WL)-0.5 • As transistor area decreases with scaling, σVt increases • Channel Length Variation • Difficulty to control the critical dimensions at sub-wavelength lithography • Large variations in the channel length (L) • Vt α exp(-L)due to short channel effects • A small variations in L results in large variations in Vt T. C. Chen et al., ISSCC06 S. Borkar et al., DAC04 Variations increase with technology scaling Introduction and Background

7. Delay distribution PASS FAIL Delay Target delay Variability and Yield • Process variations causes the device parameters to have fluctuations around their nominal values • The system parameters such as delay and power have a spread around their nominal values • This result in a percentage of the systems does not meet the required function or the required parameter constraint •  Yield loss Variability results in Yield loss Introduction and Background

8. Variability and Sub-threshold logic • Sub-threshold logic is adopted for low power consumption when performance is of secondary importance • The minimum energy occurs at the sub-threshold operating region • Variability increases in sub-threshold circuits due to the exponential relationship between the current and Vt Sub- threshold Super- threshold Energy Vt VDD Minimum Energy Variability increases in sub-threshold circuits Introduction and Background

9. Outline • Introduction and Background • Motivation and Objectives • Simulation Procedure • Results and Discussions • Conclusion Motivation and Objectives

10. Motivation • With technology scaling: • Variability is getting worse resulting in yield loss (higher cost), especially, in sub-threshold circuits. • Flip-Flops • The continued demand for low power consumption leads to sub-threshold circuit design • There are several Flip-Flops topologies which have different power and performance trade-offs • Flip-Flops designers need some design guidelines on selecting the best Flip-Flop topology suitable for their application constraints considering power, performance, and yield Motivation and Objectives

11. Objectives • The power yield improvement of the sub-threshold flip-flops is of paramount importance, especially, in applications with strict power constraints. This power yield improvement results in excess delay and energy overheads. • The questions are: • Which flip-flop topology exhibits the largest overheads ? • Which flip-flop topology exhibits the lowest overheads? Motivation and Objectives

12. Outline • Introduction and Background • Motivation and Objective • Simulation Procedure • Flip-Flops Selection and Design • Power Yield Improvement Using Gate Sizing • Results and Discussions • Conclusion Simulation Procedure

13. Flip-Flops Selection (3 topologies) • 1. Master-Slave Topology • Good hold time & Relatively high latency delay • Selected Flip-Flops: • Transmission-Gate Master-Slave Flip-Flop (TG-MSFF) : implemented in IBM PowerPC 603 processor and used in standard libraries (AMS) [1] • Modified-Clocked CMOS-Master-Slave Flip-Flop (MC2MOS-MSFF) : used in standard libraries (AMS) [2] TG-MSFF M-C2MOS-MSFF [1] G. Gerosa et al., JSSC94; [2] V. Stojanovic et al., JSSC99 Simulation Procedure

14. Flip-Flops Selection (3 topologies) • 2. Pulsed Flip-Flops • Samples the input data at a short transparency period around the clock edge • High performance • High power consumption & poor hold time • Selected Flip-Flop: • Semi-Dynamic Flip-Flop (SD-FF) [1] : • One of the fastest flip-flops structures • The most convenient structure for high performance applications SD-FF [1] F. Klass, VLSI Dig. 98 Simulation Procedure

15. Flip-Flops Selection (3 topologies) • 3. Sense-amplifier based flip-flop topology (SA-FF) • High performance at moderate power consumption • Represents a compromise between the MS-FF and the Pulsed-FF topologies • Uses differential pair architecture • Selected Flip-Flop: • Strong Arm 110 Flip-Flop (SA-FF) [1]: • implemented in the high performance WD21264 Alpha processor A comparative analysis among the selected flip-flops will aid the flip-flops designers to: Choose the best flip-flop topology based on their applications power, performance, and yield constrains [1]U. Ko et al.,ISLEPD96 Simulation Procedure

16. Flip-Flops Design • Optimum Power Delay Product (PDP) Design • All flip-flops sizes are optimized to achieve minimum EDP • The optimization process is performed by using the CFSQP (C-version Feasible Sequential Quadratic Programming) optimization package • Functional Yield Improvement Using Setup Time Margin • Monte Carlo Analysis including D2D and WID variations is conducted using industrial STMicroelectronics 65-nm Technology node. • Due to variability, the setup time of some of the flip-flops samples is violated and these samples malfunction reducing the functional yield • A setup time margin is added to improve the functional yield > 99.9% Simulation Procedure

17. Power Yield Improvement Using Gate Sizing • Main idea • Find the transistors sizes that shift the power distribution to achieve a power yield ≥ a given yield (Yo) • The power exhibits a log-normal distribution Statistical gate sizing to shift the power distribution mean Simulation Procedure

18. Power Yield Improvement Using Gate Sizing • Algorithm • Find the mean and standard deviation of the power distribution of the initially sized sub-threshold flip-flops (PO and σ ) • Using PO and σ , find the equivalent normal distribution mean and standard deviation ( μln and σln ) • Using μln and σln , find the geometric mean and standard deviation of the log-normal distribution (μg and σg ) • Using μg and σg , find the new target power distribution mean (PO ‘) n = 3 for YO = 99.87% Simulation Procedure

19. Power Yield Improvement Using Gate Sizing • Algorithm Flowchart Power Constraint (PO) Power Yield Constraint (YO) Initial gate sizing (obtained for optimum EDP) Calculate the power mean and variability (PO and σ) Calculate PO’ Calculate the gate sizing that match Po’ and minimize the delay and energy overheads Repeat if the power yield Constraint is not met Simulation Procedure

20. Outline • Introduction and Background • Motivation and Objective • Simulation Procedure • Results and Discussions • Conclusion Results and Discussions

21. The delay, energy, and EDP Overheads Required for Power Yield Improvement • SA-FF exhibits the lowest overheads . Thus, the SA-FF is recommended for sub-threshold operation. • MC2MOS-FF exhibits the highest overheads. Therefore, the MC2MOS-FF is not recommended at all for sub-threshold operation. • TG-MSFF shows lower overheads than that of the SD-FF for power yield improvement.

22. The delay, energy, and EDP Overheads Required for Power Yield Improvement • Scattered plots: TG-MSFF M-C2MOS-MSFF

23. The delay, energy, and EDP Overheads Required for Power Yield Improvement • Scattered plots: SD-FF SA-FF

24. Outline • Introduction and Background • Motivation and Objective • Simulation Procedure • Results and Discussions • Conclusion Conclusions

25. Conclusion • A comparative analysis among different sub-threshold flip-flops topologies is performed considering the required delay and energy overheads for power yield improvement . • This work demonstrates that the SA-FF is the recommended candidate for sub-threshold operation in the nanometer regime whereas the MC2MOS-MSFF is not recommended due to its large delay and energy overheads. Conclusions

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