Tri-Level-Cell Phase Change Memory (PCM): Toward an Efficient and Reliable Memory System

1. Tri-Level-Cell Phase Change Memory (PCM): Toward an Efficient and Reliable Memory System Nak Hee Seong Sungkap Yeo Hsien-Hsin S. Lee School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, GA 30332 nakhee.seong@gmail.com {sungkap, leehs}@gatech.edu Presented By: Anand Dhole Shalini Satre

2. Contents • PCM • Background and Motivation • Tri-Level-Cell (3LC) PCM • 3LC PCM in Practice • Evaluation • Conclusion

3. PCM • Background and Motivation • Tri-Level-Cell (3LC) PCM • 3LC PCM in Practice • Evaluation • Conclusion

4. Phase Change Memory (PCM) • Promising alternative memory technology • Two states • Crystalline (SET) • Amorphous (RESET) • Multi-level-cell PCM • Intermediate states • Store more data per cell

5. Single Level Cell (SLC) [1] Set Reset High resistivity Low resistivity

6. SLC vs MLC Four Storage Levels Two Storage Levels 0 1 002 012 102 112 2LC or SLC = one bit per cell 4LC = two bits per cell

7. SLC PCM SET RESET i i t t # of Cells  103 106 103 Difference

8. MLC PCM i SET RESET i i t t t # of Cells Storage Level 0 Storage Level 1 Storage Level 2 Storage Level 3  1k  1M

9. Error Model • Critical problems • Resistance Drift • Resistance of PCM cell increases over time • Soft errors • Not permanent failure • Have solutions to resolve • Soft error caused by resistance drift • Error rate is proportional to initial resistance value • Error rate is negligible in SLC PCM • In MLC PCM, resistance drift at intermediate levels • Iterative-writing mechanism • Degrades write latency • For 4LC, 4x~8x slower than that of SLC [1]

10. Resistance Drift [1] T = 1 # of Cells SET RESET Storage Level 0 Storage Level 1 Storage Level 2 Storage Level 3  Programmed Boundaries Decision Boundaries

11. Resistance Drift T = 2 # of Cells SET RESET Storage Level 0 Storage Level 1 Storage Level 2 Storage Level 3 

12. Resistance Drift T = 4 # of Cells SET RESET Storage Level 0 Storage Level 1 Storage Level 2 Storage Level 3 

13. Resistance Drift T = 8 # of Cells SET RESET Storage Level 0 Storage Level 1 Storage Level 2 Storage Level 3  Drift-induced Soft Errors!!!

14. Drifted Resistance • Power Law Equation

15. Proposed Solution • Proposed tri-level-cell PCM • Soft error rate matches that of DRAM • Gain performance of SLC PCM

16. PCM • Background and Motivation • Tri-Level-Cell (3LC) PCM • 3LC PCM in Practice • Evaluation • Conclusion

17. Background and Motivation • Flash Memory w.r.t. PCM • Switching mem. ele. requires more voltage & time. • Degrades more rapidly • More susceptible to radiation • PCM w.r.t NAND • Better read/write latency. • Consumes significantly less read/write energy. • PCM Advantages • Higher information density. • Cheaper when in mass production.

18. Background and Motivation cont… • MLC PCM • Many intermediate states between SET and RESET • E.g. 8LC PCM stores three bits per cell • Soft error rate(SER) is higher than that of DRAM • SER increases over time along with resistance • Error correction Methods • Time-aware error correction scheme • Scrub mechanism

19. Background and Motivation cont… • Time-aware error correction scheme [3] • Uses extra cells for storing predefined reference resistance values • While reading, reference values are used to compensate the resistance drift in corresponding cell. • Reduced SER from 10-3 ~ 10-1 to 10-4 ~ 10-2

20. Background and Motivation cont… • Scrub Mechanism [2] • Reduced 99.6% of uncorrectable errors • Memory controller spend more time in scrubbing • DRAM-style self refresh [3] • Cells with correct information also gets refreshed • Higher chip-level power • Frequent write decreases lifespan • Slower responsiveness

21. PCM • Background and Motivation • Tri-Level-Cell (3LC) PCM • 3LC PCM in Practice • Evaluation • Conclusion

22. 3LC PCM • Each cell has three storage levels • Removed most error-prone state from 4LC PCM i.e. Third storage level • Drift is proportional to resistance • Removes errors generated by third as well as most of the errors generated by second storage level

23. 3LC PCM Two Storage Levels 0 1 Three Storage Levels 03 13 23 2LC or SLC = one bit per cell Four Storage Levels 3LC 002 012 102 112 ~ 1.5 bits per cell ≠three bits per cell 4LC = two bits per cell Binary System TernarySystem

24. PCM • Background and Motivation • Tri-Level-Cell (3LC) PCM • 3LC PCM in Practice • Evaluation • Conclusion

25. 3LC PCM • 4-level cell PCM • unreliable • Tri-level cell PCM • Removing the most error-prone state i i i t t t L2 L0 L1

26. Bandwidth Expanded 3LC PCM i Relaxing programming range Reducing programming latency Increasing write bandwidth or t SET RESET i i i t t t # of Cells L2 L0 L1 L1

27. Configuration variable of 4LC PCM Configurationvariable of 3LC PCM

28. Efficient Conversion Method [1] • In theory 11 bits of binary = 2048 states 7 ternary cells = 2187 states ~94% utilization • Proposed approach 3 bits of binary = 8 states 2 ternary cells = 9 states ~89% utilization Notation: <3,2> conversion

29. Number Mapping Method 00 000 01 10 001 010 100 02 11 20 011 101 110 12 21 111 22 Binary Ternary

30. ECC for Tri-Level-Cell PCM Single Bit Error Single Bit Error Ternary Binary • Legacy ECC for binary can be used • Simple (72, 64) Hamming Code • Memory controller requires minimal change

31. PCM • Background and Motivation • Tri-Level-Cell (3LC) PCM • 3LC PCM in Practice • Evaluation • Conclusion

32. Drift Induced Error Rate

33. Information Density Data block size- 256 bits Bits Per Cell Number of Correctable Bits

34. PCM • Background and Motivation • Tri-Level-Cell (3LC) PCM • 3LC PCM in Practice • Evaluation • Conclusion

35. Conclusion [1] • Results (over 4LC PCM) • 105 lower soft error rates • 36.4% performance improvement • Results (over SLC PCM) • 1.33x higher information density

36. References • Nak Hee Seong, Sungkap Yeo, Hsien-Hsin S. Lee, "Tri-Level-Cell Phase Change Memory: Toward an Efficient and Reliable Memory System",ISCA'13 • M. Awasthi, M. Shevgoor, K. Sudan, B. Rajendran, R. Balasubramonian, and V. Srinivasan, “Efficient Scrub Mechanisms for Error-Prone Emerging Memories,” in Proceedings of the International Symposium on High Performance Computer Architecture, 2012.vol. 19, no. 8, pp. 1357–1367, 2011 • W. Xu and T. Zhang, “A time-aware fault tolerance scheme to improve reliability of multilevel phase-change memory in the presence of significant resistance drift,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 8, pp. 1357–1367, 2011. • T. Nirschl, J. Phipp, T. Happ, G. Burr, B. Rajendran, M. Lee, A. Schrott, M. Yang, M. Breitwisch, C. Chen et al., “Write strategies for 2 and 4-bit multi-level phase-change memory,” in IEEE International Electron Devices Meeting (IEDM), 2007, pp. 461–464. • N. Papandreou, H. Pozidis, T. Mittelholzer, G. Close, M. Breitwisch, C. Lam, and E. Eleftheriou, “Drift-tolerant multilevel phase-change memory,” in 2011 3rd IEEE International Memory Workshop (IMW). IEEE, pp. 1–4. • R. Hamming, “Error detecting and error correcting codes,” Bell System Technical Journal, vol. 29, no. 2, pp. 147–160, 1950.