Efficient Power Estimation Algorithm for Integrated Circuits

1. 18-743Project Report IIRIPE: A Rapid Implication-based Power Estimator Sunil Motaparti, Gaurav Bhatia

2. OUTLINE • Problem to Solve • Motivation • Approach • Previous Milestone • Current Milestone • Milestone Schedule

3. PROBLEM TO SOLVE • Gate Level Power Estimation • Computing Average switching activity of a circuit gives a somewhat accurate estimation of power consumption • Consideration of spatio-temporal correlations yield more accurate estimations of the average switching activity • Done using Markov chains which compute step-transition probabilities (as discussed in lecture)

4. MOTIVATION • Some of the Early work has not dealt with reconvergent fanout • More recent work that deals with the above has involved using OBDD’s which are computation intensive and slow • Most of the approaches have not been line independent and hence an algorithm which can reduce this dependency is desirable

5. APPROACH • Static Learning (also called Static Logic Implication) can be used • Find implications of setting a line l to a particular value v • Direct Implications • Forward / Backward Simulation • Indirect Implications • Contrapositive Law • Extended Backward Implication • Iterative • Implemented using set operations • Implicitly captures the reconvergent fanout structures in the circuit

6. APPROACH (contd.) • Computing Step Transition Probabilities • Find Crucial Nodes • Sets of Nodes through which paths from primary inputs to lines have to pass through • Dominators • Min-Cut • Limit size to 5-6 • For a set of n crucial nodes, we have 2n combinations of values for current clock cycle and 2n combinations of values for next clock cycle • We have 22n pairs of distinct combinations of values • For each pair, we update the transition counts on each line that is present in the implication sets of the current and next combinations by doing set union and set intersection operations • we compute step transition probability using the formula:- stp(x) = (# of times x switched for 22n pairs) / 22n • Mostly Line Independent • For nodes that were not covered by any set of crucial nodes, we compute the step transition probabilities one by one

7. PREVIOUS MILESTONE • Finished building event-driven simulator • Finished Parser • Reads benchmarks in structural Verilog and ISCAS89 formats • Implemented certain parts of implication engine (fully tested and debugged) • Built Forward Implication part • Built Transitive Implication part • Finished pseudo-code for the rest of the engine

8. CURRENT MILESTONE • Finished implementation and testing of the full implication engine • Implemented all types of implications discussed • Tested on various benchmarks such as c17, c432, c5315, c7552 • Execution times for finding implications are usually low with the execution time for the largest circuit being 80.39s on a 750Mhz machine. • Currently conducting experiments to get an approximate size of the crucial node computation required • Will start working on crucial node computation implementation after obtaining results

9. PROBLEMS SO FAR • Parser assumption • Parser assumes that a particular input to a gate in a netlist has been instantiated or described before its first use • Obtained utility to convert benchmarks to adhere to the above assumption, have to make it adapt to the structural verilog format

10. MILESTONES • 1st Report • Build event-driven simulator and various parts of the implication engine • 2nd Report • Finish building implication engine • 3rd Report • Implement Crucial-node computation and finish complete implementation • Final Report • Optimizations (if above milestones are met)

11. Questions ?