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Follow two instructions through the pipeline individually and combined. Practice with add and load instructions, analyze stages from IF to WB. Note: the rightmost multiplexer is inverted.
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Pipeline In Use • We’ll follow two instructions through the pipeline, first separately, then together. • add $7,$2,$3, where $2 = 35 and $3 = 62 • lw $4, 28($5), where $5=56 and memory location 84 stores 20 • add instruction at address 40; lw at 44 • Note: rightmost multiplexor is inverted
add $7,$2,$3 – IF stage 40 0 44 40 add
add $7,$2,$3 – ID stage 10 000 000000 1100 2 35 3 62 100000 7
add $7,$2,$3 – EX stage 10 000 35 0 62 97 1 0010 62 100000 10 7 7 1
add $7,$2,$3 – MEM stage 10 0 0 0 97 7
add $7,$2,$3 – WB stage 1 0 7 97 97
lw $4, 28($5) – IF stage 44 0 48 44 lw
lw $4, 28($5) – ID stage 11 010 100011 0001 5 56 28 4
lw $4, 28($5)– EX stage 11 010 56 1 84 1 0010 28 28 4 00 4 0
lw $4, 28($5)–– MEM stage 11 0 0 84 20 1 4
lw $4, 28($5)–– WB stage 1 1 20 4 20
add – IF stage 40 0 44 40 add
lw – IF stage, add – ID stage 10 000 000000 1100 44 0 48 2 35 44 3 62 lw 100000 7
lw – ID stage, add – EX stage 11 10 010 100011 000 0001 5 56 35 62 97 0010 62 28 100000 4 10 7 7 1
lw – EX stage, add – MEM stage 11 010 10 0 0 56 1 84 1 0010 28 28 0 97 4 00 4 7 0
lw – MEM stage, add – WB stage 11 0 1 0 0 84 20 7 97 97 1 4
lw - WB stage 1 1 20 4 20