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CA406. Computer Architecture Memory Management Units. Memory Management Unit. Physical and Virtual Memory Physical memory presents a flat address space Addresses 0 to 2 p -1 p = number of bits in an address word User programs accessing this space Conflicts in multi-user (eg Unix)
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CA406 Computer Architecture Memory Management Units
Memory Management Unit • Physical and Virtual Memory • Physical memory presents a flat address space • Addresses 0 to 2p-1p = number of bits in an address word • User programs accessing this space • Conflicts in • multi-user (eg Unix) • multi-process (eg Real-Time systems) • systems • Virtual Address Space • Each user has a “private” address space • Addresses 0 to 2q-1 • q and p not necessarily the same!
Memory Management Unit • Virtual Address Space • Each user has a “private” address space
Virtual Addresses • Memory Management Unit • CPU (running user programs) emits Virtual Address • MMU translates it to Physical Address • Operating System allocates pages of physical memory to users
Virtual Addresses • Mappings between user space and physical memory created by OS
Memory Management Unit (MMU) • Responsible forVIRTUAL ç PHYSICALaddress mapping • Sits between CPU and cache • Cache operates on Physical Addresses(mostly - some research on VA cache) VA PA MMU PA Main Mem CPU Cache D or I D or I
MMU - operation • OS constructs page tables -one for each user • Page address from memory address selects a page table entry • Page table entry contains physical page address
MMU - Virtual memory space • Page Table Entries can also point to disc blocks • Valid bit • Set: page in memory address is physical page address • Cleared: page “swapped out” address is disc block address • MMU hardware generates page faultwhen swapped out page is requested • Allows virtual memory space to be larger than physical memory • Only “working set” is in physical memory • Remainder on paging disc
MMU - Page Faults • Page Fault Handler • Part of OS kernel • Finds usable physical page • LRU algorithm • Writes it back to disc if modified • Reads requested page from paging disc • Adjusts page table entries • Memory access re-tried
MMU - Page Faults • Page Fault Handler • Part of OS kernel • Finds usable physical page • LRU algorithm • Writes it back to disc if modified • Reads requested page from paging disc • Adjusts page table entries • Memory access re-tried • Can be an expensive process! • Usual to allow page tables to be swapped out too! • Page fault can be generated on the page tables!
MMU - practicalities • Page size • 4 kbytes k = 13 • p = 32 • p - k = 19 • So page table size • 219 = 0.5 x 106 • Each entry 4 bytes • 2 Mbytes! • Page tables can take a lot of memory! • Larger page sizes reduce page table sizebut can waste space • Access one byte whole page needed!
MMU - practicalities • Page tables are stored in main memory • They’re too large to be in smaller memories! • MMU needs to read PT for address translation • Address translation can require additional memory accesses! • >32-bit address space?
MMU - Virtual Address Space Size • Segments, etc • Virtual address spaces >232 bytes are common • Intel x86 - 46 bit address space • PowerPC - 52 bit address space • PowerPCaddressformation
MMU - Protection • Page table entries • Access control bits • Read • Write • Read/Write • Execute only • Program - “text” in Unix • Read only • Data • Read write
MMU - Alternative Page Table Styles • Inverted Page tables • One page table entry (PTE) / page of physical memory • MMU has to search for correct VA entry • PowerPC hashes VA PTE address • Hashing collisions • PTEs are linked together • PTE contains tags (like cache) and link bits • MMU searches linked list to find correct entry • Smaller Page Tables / Longer searches
MMU - Sharing • Can map virtual addresses from different user spaces to same physical pages • Sharing of data • Commonly done for frequently used programs • Unix “sticky bit” • Text editors, eg vi • Compilers • Any other program used by multiple users • More efficient memory use • Less paging • Better use of cache
Address Translation - Speeding it up • Two+ memory accesses for each datum? • Page table 1 - 3 (single - 3 level tables) • Actual data 1 • system running slower than an 8088? • Translation Look-Aside Buffer • (TLB or TLAB) • Small cache of recently-used page table entries • Usually fully-associative • Can be quite small!
Address Translation - Speeding it up • TLB sizes • MIPS R4000 1992 48 entries • MIPS R10000 1996 64 entries • HP PA7100 1993 120 entries • One page table entry / page of data • Locality of reference • Programs spend a lot of time in same memory region • TLB hit rates tend to be very high • 98% • Compensate for cost of a miss (many memory accesses!)
