Efficient Selection of b, t, m, e for Light Particles in High Pile-up Collisions

1. b FTK FTK - Outline e b m t b m b b t h e t More details on https://cds.cern.ch/record/1552953/files Efficient selection of b, t, m, e: to be efficient on light particles (W, Z, H….) in terrific pileup • Why FTK? Timing and Event complexity @High Luminosity • FTK architecture • Milestones & Contributions from Italy in particular from Pisa • Physics case:b-jets, tau-jets, missing ET, primary vertexing….. • R&D for the future: Phase II and imaging outside HEP

2. Why FAST TRACKING is IMPORTANTfor TRIGGER @ HADRON COLLIDERS WITH HIGH PILE-UP 109 QCD Light quarks Pile-up: 25 eventi @1034 cm-2s-1 40 MHz coll. Rate 75 eventi @3x1034 cm-2s-1 40 MHz coll. Rate Phase I Hard Life! 107 105 Eventi/s per L = 1034 cm-2s-1 103 s 10 One of 1012 RARE EVENTS 10-1 10-3 H S1/2 (TeV)

3. 30 minimum bias events + H->ZZ->4m L1-L2 early tracking: a tough problem Where is the Higgs? m m m m Tracks with Pt>2 GeV FTK 30 minimum bias events + H->ZZ->4m @LHC (both CMS & Atlas) tracking is missing @L1 and late @L2 Where is the Higgs? m m Help! m m Tracks with Pt>2 GeV

4. L1 jet Threshold = 20 GeV 3 1034 FTK Global Tracking PT>1 GeV 25 Microsec TrigSiTrack Time per RoI 25 msec per jet 1034 3 1034 0 20 40 60 Execution time msec 0 40 80 120 Execution time msec FTK between L1 & L2 extremely important @ High Luminosity Timing WH events @31034 average of 40 jet > 70 Gev per event P0 P1 P2 SCT Layers # of ROD Hits Y intercept: Hard scattering! negligible compared to pileup

5. FTK @ Intermediate Luminosity – late 2015 Only the barrel will be covered • Hardware & Physics test before full detector coverage; test on real conditions of the detector; • large impact on the whole trigger. • Study b-tag and tau-tag trigger (Z0→bb, tau-tau+QCD backg). Level-2 and Event Filter algorithms in CPUs have to be modified to take into account the new track availability at L2 start. • Level-1 has to be re-studied also for Phase 1. • Global Level-1 designed for Phase 1. • Level-1 & FTK optimized together. • Availability of new phase space regions, like enlargement of phase space for “Hadronic Channels”. • Not included in the baseline trigger, neither in CMS neither in Atlas. • There is a new interest in this area: 4 bs events….

6. Why L1-L2 early TRACKING is IMPORTANT? The calorimeter tower integrates energy from all the particles, also from Pileup! Tracking separates HARD SCATTERING from Pileup! Hard scattering ID: primary vertex identified at L2 start  Isolation with tracks from rightvertex Only 7 vertices: imagine 100! 10 cm/100=1 mm z Tracking more stable than calorimetric isolation against pile-up!

14. ITALIAN DUTIES for 3x10**34 Associative Memory History • 90’s Full custom VLSI chip – 0,7 mm (INFN-Pisa) patterns, 6x12 bit words each (F. Morsani et al., The AM chip: a Full-custom MOS VLSI Associative memory for Pattern Recognition, IEEE Trans. on Nucl. Sci.,vol. 39, pp. 795-797 (1992).) • 1998 FPGA (Xilinx 5000) for the same AMchip (P. Giannetti et al., A Programmable Associative Memory for Track Finding, Nucl. Intsr. and Meth., vol. A 413/2-3, pp.367-373, (1998) ). • 1999 first standard cell project presented at LHCC • 2006 AMChip 03 Standard Cell UMC 0,18 mm, 5k patterns in 100 mm2 for CDF SVT upgrade total: AM patterns (L. Sartori, A. Annovi et al., A VLSI Processor for Fast Track Finding Based on Content Addressable Memories, IEEE TNS, Vol 53, Issue 4, Part 2, Aug. 2006) • 2012 AMchip04 (Full custom/Std cell) TSMC 65 nm LP technology, 8k patterns in 14mm2 Pattern density x12. First variable resolution implementation. (F. Alberti et al, 2013 JINST & C01040, doi:10.1088/1748-0221/8/01/C01040) • 2013 AMchip05,4k patterns in 12 mm2 a further step towards final AMchip version. Serialized I/O buses at 2 Gbs, further power reduction approach. BGA 23x23 package. • 2014 AMchip06: 128k patterns in 180 mm2. Final version of the AMchip for the ATLAS experiment.

15. CPU vme AM10+….. AM15+….. AM14+….. AM13+…… AM9+…... AM12+….. AM11+….. AM8+….. AM7+TSP+DO+TF+HW AM6+TSP+DO+TF+HW AM4+TSP+DO+TF+HW AM5+TSP+DO+TF+HW AM0+TSP+DO+TF+HW AM3+TSP+DO+TF+HW AM2+TSP+DO+TF+HW AM1+TSP+DO+TF+HW 11LayFit+ HW final 11LayFit+ HW final 11LayFit+HW 11LayFit+HW ITALIAN DUTIES for 3x10**34 DATA FORMATTER FRASCATI: mezzanine Processing Unit Italy+Chicago AUX card FERMILAB Motherboard

16. DESIGN AND TEST OF the mini@sic with SERDES

18. b FTK e b m t b m b b t h e t FTK Physics Case taus bs MET PV

19. L1: 2TAU12I_TAU20I_J25:DR28 BEST EFFICIENCYBEST REJECTION

20. RSIG RI RISO Jet axis leading PT track TAUs Identification @L2 ! Perfect for tracking

21. First of all: require that the JET & at least a tau match the PV 60% of background ROIs have no track pointing to PV Background mainly multiple 22 Not Mercedes events! 97% efficient 50% rejection 10% of background taus has no track pointing to PV

22. BUT ALSO AT L1 we can separate BOOSTED HIGGS and 2 2 QCD L1 Topological Trigger Not boosted Higgs boosted Higgs QCD Dphi (tau-tau)

24. B-tagging

25. FTK track refitted by CPUs

28. MET TRIGGER

29. MET TRIGGER

30. ATLAS L1 Topological processor

31. R&D for phase II

34. Conclusions • There is a lot of space in a wide range of activities: • Analysis of FTK-selected samples • Trigger studies for better FTK exploitation: L1 & L2. • Hardware & Software development for tests • Software and hardware team for commissioning • Data taking and mantainance • R&D for phase II – chip & board design • Wide chances for important responsibilities.

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