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Conception d’un processeur DSP faible énergie en logique ternaire

Conception d’un processeur DSP faible énergie en logique ternaire. Université de Rennes - ENSSAT IRISA sentieys @enssat.fr. O. SENTIEYS, M. ALINE, E. KINVI-BOH. FTFC 2003, Paris, 14-16 Mai 2003. Outline. Motivations MVL implementation with SUS-LOC Principle of SUS-LOC structures

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Conception d’un processeur DSP faible énergie en logique ternaire

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  1. Conception d’un processeur DSP faible énergie en logique ternaire Université de Rennes - ENSSAT IRISA sentieys@enssat.fr O. SENTIEYS, M. ALINE, E. KINVI-BOH FTFC 2003, Paris, 14-16 Mai 2003

  2. Outline • Motivations • MVL implementation with SUS-LOC • Principle of SUS-LOC structures • Characterization at the transistor-level • Characterization at the gate-level • Design of a ternary DSP structure • Experimental results and comparisons • Conclusion and future works

  3. Multiple Valued Logic (MVL) • Currently, computers and other electronic devices run as 101101… binary logic with 2 logical states: 0, 1 • MVL can offer: • Many logical states: 0, 1, 2, 3, … • More complex functions • in less time, power and area than binary ? • MVL circuit structure ?

  4. MVL Circuits Structures • Current-Mode CMOS Logic (CMCL) [3] • Voltage-Mode nMOS technology [16] • QCD or CCD technology [1][2] • Supplementary Symmetrical Logic Circuit Structure (SUS-LOC) [8][11] • Voltage-Mode (i.e. CMOS) • Energy Efficient • A new promising structure

  5. A decrease of passive parasitic values A decrease in required power (dynamic and static) Ability to perform multiple logic functions in one operation e.g. (A+B) AND D Security, confidentiality An increase in data density Interconnections e.g. 40 bits become 25 terts1 (37.5% reduction), or 20 4L-digits More bandwidth with a reduced clock rate 16 bits f 10 terts 1 Mbit/s  750 ktert/s Reduced package size Technical advantages of SUS-LOC MVL circuits and devices 1 terts stands for ternary digits

  6. V0 V1 V2 Inputs Output N0 N1 N2 SUS-LOC principle SUS-LOC structures Transistor library Characterization Process • Principle • Ternary case: radix r = 3 • Logic states: {0,1,2} • r-1 different sources of power • e.g. {0V, 1.25V, 2.5V} • r-1 independent controllable paths VHDL Performance modeling

  7. X S 0 1 2 2 1 0 F 0 1 1 2 0 2 SUS-LOC principle SUS-LOC structures Transistor library Characterization Process • Example: ternary inverter • Truth Table • N(x) = <2 1 0> VHDL Performance modeling

  8. SUS-LOC principle Transistor Library Transistor library Characterization Process • Use of depleted and enhanced MOS transistors • SPICE models • 0.25m technolgy • 2m SOI technolgy (UCL) VHDL Performance modeling Id(Vgs) MbreakPD MbreakND MbreakP MbreakN MbreakP+ MbreakN+

  9. A S B CGAND3 SUS-LOC principle Logic Functions Transistor library Characterization Process • Ternary CGAND • Complementing Generalized AND • CGAND(X,Y) = N(MAX(x,y)) VHDL Performance modeling

  10. CGAND

  11. CGAND

  12. XCIRCUIT MVLStim Hierarchical netlist ELDO Report file MVLCara SUS-LOC principle Characterization Transistor library Characterization Process • Transistor-level Validation • Delay and Power Characterization VHDL Performance modeling

  13. SUS-LOC principle Characterization Transistor library Characterization Process • Transistor-level Validation • Delay and Power Characterization • e.g. Ternary vs Binary Inverter VHDL Performance modeling

  14. Design of a ternary standard cell library • CGAND, CGOR, Inverters, … • Mux, Tri-state • LATCH, D Flip-Flop • SRAM memory cell and sense amp. • Arithmetic components • HA, Pi, Gi, CLA, multiplier • 1T-Shifter

  15. SUS-LOC principle Gate-level Transistor library Characterization Process • VHDL package for simulation • STD_TERNARY_LOGIC • VHDL set of tools for architecture- and gate-level estimations • Power, Delay • Gate-level simulation VHDL Performance modeling ELDO simulation Report file VHDL Package Power consumption Delay VHDL Gate level simulation Description.vhd

  16. Outline • Motivations • MVL implementation with SUS-LOC • Design of a ternary DSP structure • Experimental results and comparisons • Conclusion and future works

  17. L EB L CB L DB H H T register A B C D S B A C D T T D A C D A A(H) B(H) MUX MUX MUX H MUX MUX 0 MUX Barrel shifter A B H Multiplier A U B S L M MUX N Legend : A Accumulator A B Accumulator B C CB data bus D DB data bus E EB data bus M MAC unit S Barrel shifter T T register U ALU E H ALU Adder Bus width : L : 16 bits, 10 terts N : 32 bits, 20 terts H : 40 bits, 25 terts H A ternary vs. binary DSP

  18. Interconnections • Bus structure • 16 bits become 10 terts • 40 bits become 25 terts • Activity of wires • Binary: • Ternary:

  19. SRAM Memory • Transistor equivalent, faster access time • Up to 50% in energy reduction

  20. Arithmetic structures • e.g. 40-bit vs. 25-tert Sklansky Adder • 100 vs. 54 Brent and Kung cells

  21. Conclusion and future works • SUS-LOC concepts for a ternary DSP • Experiments on representative modules • Comparison: SUS-LOC vs. CMOS circuits • High energy efficiency • Future works • Prototype chip with an SOI technology • 3L and 4L SRAM and Flash memories • Optimization of arithmetic structures • …

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