ATLAS Liquid Argon Calorimeter: Read Out Driver Board status and plans

1. ATLAS Liquid Argon Calorimeter:Read Out Driver Board status and plans Imma Riu Université de Genève Rencontres de Bossey 12 July 2002 • Outline: • Introduction • The LArgon readout architecture • ROD system description • Status and plans • Conclusions ATLAS LArgon calorimeter: ROD Board status and plans

2. Introduction ATLAS detector • The ATLAS Liquid Argon calorimeter is divided into: • Barrel calorimeter (EMB) • Hadronic endcaps (HEC) • Electromagnetic endcaps (EMEC) • Forward calorimeter (FCAL) • In total, around 190 000 channels are to be read out. ATLAS LArgon calorimeter: ROD Board status and plans

3. EM Endcap prototype ATLAS LArgon calorimeter: ROD Board status and plans

4. The challenge of the electronics • Large dynamic energy range: [50 MeV - 3TeV] 16 bits ! • The bunch crossing (BX) rate at LHC is 40 MHz (each 25 ns): For a signal of 600 ns, the pile-up takes up to 24 BXs. • Required relative energy resolution: ~ 10% / E: Pile-up and electronic noise should be minimized. Good calibration of the electronics response. Noise dependence on luminosity and peak time Signal after shaping Different BXs Detector signal shape ATLAS LArgon calorimeter: ROD Board status and plans

5. Detector: Radiation environment FEB FEB FEB FEB FEB FEB FEB FEB FEB FEB FEB FEB FEB FEB FEB FEB USA15: Radiation free ROD ROD ROD ROD ROD ROD ROD ROD ROD ROD The LArgon Read Out Architecture HEC EMEC FCAL EM Barrel EMEC HEC FCAL 5 3 6 1 2 4 5 6 FEB FEB FEB Front End Boards FEB Read Out Driver Boards DAQ ATLAS LArgon calorimeter: ROD Board status and plans

6. FEB and ROD boards functionality Located in the detector Located in USA15 room FEB FEB FEB FEB FEB ROD FEB FEB FEB 8 optical fiber 1.6 Gbit/s ~100m 100 kHz event rate • Radiation tolerant board. • 128 channels / FEB. • Fast signal shaping (~ 50 ns). • Five digitized points (12 bits) using three gains in the ratio 1/10/100. • Gain selection (2 bits). • LArgon needs ~1600 FEBs. • Event processing time  10s. • Computation of time, energy and shape quality flag (2). • Use of optimal filtering algorithm. • Use of Digital Signal Processors (DSP). • Generation of the ‘busy’ signal. • LArgon needs ~200 RODs. ATLAS LArgon calorimeter: ROD Board status and plans

7. ROD module: • ROD mother board (MB) • Uses G-link chips for deserializing the data from the optical fiber. • Includes TTCrx ASIC which provides Trigger-Time-Control information: LHC clock, event and bunch crossing identifiers, ATLAS trigger type. • Uses SDRAMs for storing raw data (for online histograms) • Uses programmable chips (FPGA). • 4 processing units (PU) mounted on top of the ROD mother board. • Include Digital Signal Processors (DSP) chips. • 2 DSP / PU. [1 DSP per FEB] • Use FPGA chips as well. Nevis Labs ROD physical description • ROD system: • Input:8 optical fibers with FEB raw data (16 bits @ 80 MHz) • Output:4 optical fibers with ROD calculations (32 bits @ 40 MHz) • It consists of: • 9U VME64x board: ROD module (14 RODs / crate at maximum) • 9U VME64x board: Transition Module ATLAS LArgon calorimeter: ROD Board status and plans

8. Read Out Driver Board VME control Processing Unit Glink SDRAM receiver Output Controller staging FPGA Glink Ser receiver Processing Unit Glink receiver SDRAM staging FPGA Output Controller Glink Ser receiver Processing Unit Glink receiver SDRAM staging FPGA Output Controller Glink Ser receiver Processing Unit Glink receiver SDRAM staging FPGA Output Controller TTC Glink receiver Ser ATLAS LArgon calorimeter: ROD Board status and plans

9. Processing Unit FIFO Input FPGA DSP Output FPGA VME TTC Input FPGA DSP FIFO ATLAS LArgon calorimeter: ROD Board status and plans

10. ROD at the beginning of LHC VME control Processing Unit Glink SDRAM receiver Output Controller staging FPGA Glink Ser receiver Glink receiver SDRAM staging FPGA Output Controller Glink Ser receiver Processing Unit Glink receiver SDRAM staging FPGA Output Controller Glink Ser receiver Glink receiver SDRAM staging FPGA Output Controller TTC Glink receiver Ser ATLAS LArgon calorimeter: ROD Board status and plans

11. VME control Processing Unit Glink SDRAM receiver Output Controller staging FPGA Glink Ser receiver Processing Unit Glink receiver SDRAM staging FPGA Output Controller Glink Ser receiver Processing Unit Glink receiver SDRAM staging FPGA Output Controller Glink Ser receiver Processing Unit Glink receiver SDRAM staging FPGA Output Controller TTC Glink receiver Ser Status of the ROD ATLAS LArgon calorimeter: ROD Board status and plans

12. Processing Unit FIFO Input FPGA DSP Output FPGA VME TTC Input FPGA DSP FIFO ATLAS LArgon calorimeter: ROD Board status and plans

13. bga chip Delicate points • Cooling of G-link chips: • 35 ºC at maximum for 80 MHz clock frequency. • Cooling with water or air are being studied. • For money saving, ‘staging’ is implemented: • Half of the PUs will be used at the beginning of LHC. • The DSP processes 128*2 channels. • PCB routing with multiple ball-grid-array (bga) chips. • The output goes through serializer/de-serializer at 280 MHz. ATLAS LArgon calorimeter: ROD Board status and plans

14. Built in 2000. Board frequency: 40 MHz. 2 optical receivers as mezzanine in TM. 1 Output Slink in the Transition Module. 4 PUs: 1 DSP/PU, 64 channels/DSP . Used in Test Beams and for tests of PU. To be built in 2002. Parts of the board at 80 MHz. 8 optical links integrated in the ROD. 4 Outputs Slink in the TM. 4 PUs: 2 DSP/PU, 128 channels/DSP. Need of four times less ROD modules. Sending of data serialized LVDS at 280 MHz to the TM. (test in Geneva ok) Addition of the staging FPGAs. Use of ball-grid-array chips. Past experience in Geneva ROD demonstrator ROD prototype Annie, Daniel, Ilias, Lorenzo ATLAS LArgon calorimeter: ROD Board status and plans

15. ROD Demo Transition Module PU 1 Input Link Receiver PU 2 Input Link Receiver PU 3 Output Link Transmitter PU 4 ATLAS LArgon calorimeter: ROD Board status and plans

16. Plans and milestones  • Decision of the DSP chip: Done (DSP TI 6414) • ROD preliminary design review: September 2002 (planned by Jan. 2002) • Prototype production: Oct/Nov 2002 • Pre-series production: May 2003 • PRR (production readiness review) : Oct/Nov 2003 (planned by April 2003) • Series production: January 2004 ATLAS LArgon calorimeter: ROD Board status and plans

17. Geneva ROD group • Manpower: • Engineers: • Daniel La Marra: engineer responsible of the ROD module • Annie Leger • Physicists: • Alain Blondel: project leader • Imma Riu: physicist responsible • Present responsibility: • To finish the ROD mass production by 2004. • Possible next steps: • Take part on the commissioning of the system. • Participate in the DAQ system for the RODs. ATLAS LArgon calorimeter: ROD Board status and plans

18. Conclusions • The ROD project is ongoing well in Geneva with the collaboration of LAPP and Nevis. • The Geneva group is getting ready for the preliminary design review in September 2002: finishing schematics and writing documentation. • The ROD mother board mass production is expected to be finished in 2004. ATLAS LArgon calorimeter: ROD Board status and plans