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High Frequency Model of Sub-100nm High-k RF CMOS. ○M. Nakagawa 1 , J.Song 1 , Y. Nara 2 , M. Yasuhira 2 *, F. Ohtsuka 2 , T. Arikado 2 ** , K. Nakamura 2 , K. Kakushima 1 , P. Ahmet 1 , K. Tsutsui 1 and H. Iwai 1 1 Tokyo Institute of Technology,
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High Frequency Model of Sub-100nm High-k RF CMOS ○M. Nakagawa1, J.Song1,Y. Nara2, M. Yasuhira2*, F. Ohtsuka2, T. Arikado2**, K. Nakamura2, K. Kakushima1, P. Ahmet1, K. Tsutsui1 and H. Iwai1 1 Tokyo Institute of Technology, 4259, Nagatsuta-cho,Midoriku,Yokohama,226-8502 Japan 2 Semiconductor Leading Edge Technologies, Inc.(SELETE),Japan * Current affiliation: Matsushita Electric Industrial Co.Ltd., Japan **Current affiliation: Tokyo Electron LTD., Japan
Background ~RF technology~ RF Technology is necessary in future ubiquitous society and broadband society RF CMOS can be applied Fig.1 Application spectrum : ITRS2005 • Miniaturization of MOSFET improves RF characteristics • CMOS technology apply to RF application • Low cost • Low power dissipation and high integration
High-k and RF CMOS Igs Igd Igcs Igcd Igb ε(0) Electronic polarization Orientation polarization Ionic polarization 1/τ ω0 ωe Limit of miniaturization draws near !! One is the limit of thin film of gate insulator Electrical isolation breaks down leading to high dissipation High-k insulator resolves this problem High-k is hot technology in future MOSFET Leakage current But….. Concerns about High-k MOSFET in RF region ①Fall of dielectric constant in RF region by dielectric dispersion --- High-k is not High-k in RF region? ②Degradation of RF characteristics by lower mobility ③ High interface state Dielectric dispersion
Device structure silicide HfSiON SiN Si HfSiON MOSFET structure silicide SiON SiN Si SiON MOSFET structure M1 G G G G G VIA1 STI S D S D S 63.9nm 61.7nm 62.3nm 65.5nm 65.3nm • HfSiON (EOT=1.5nm) • SiON (EOT=1.5nm) • Gate Length Lg HfSiON(64nm) SiON(51nm) • Number of finger 12(W=5μm) Increasing gate width with multi gate finger, the gate resistance become small Nf: Number of finger
DC characteristics and fT, fmax SiON SiON SiON HfSiON Id[A] Id[A] gm HfSiON HfSiON Vd (V) Vg (V) Vg (V) SiON:L/W=51nm/60mm HfSiON:L/W=64nm/60mm H21[dB] Ugain[dB] • SiON device has better DC characteristics due to electron mobility • fT: SiON device is higher than HfSiON device • fmax: There are little difference between two devices Freq Freq SiON ft = 155GHz HfSiON ft= 131GHz SiON fmax = 53GHz HfSiON fmax= 58GHz
fT,fmax@Wf=2um [dB] [dB] HfSiON: Lg=58.6nm SiON: Lg=58.6nm H21 H21 Ugain Ugain Wf=2um Wf=2um Frequency [GHz] Frequency [GHz] fT=151.36 [GHz] fT=175.79 [GHz] [GHz] fmax=123.03 [GHz] fmax=120.23 [GHz] fT fmax Gate length [nm] Fig. Gate length dependency Finger length Wf [um] Morifuji, et al., VLSI technology 1999, pp 163-164 • High fmax is gotten as simulation result indicates • ft grows with gate length, however fmax falls down with gate length
How to estimate gate capacitance gox Rg Rg Rd G D Cgate Cgate Rs Z11 gox S Rseries ∋ Rs, Rd Most simple equivalent circuit @Vg=1.5V, Vd=0V Z11=Rg+1/(jωCgate+gox)+Rseries Cgate=imag(Z11-Rg-Rseries)-1 Gate capacitance is got by deembedding series resistance from measured Z11
High frequency gate capacitance measurement Vg[V] 10GHz 20GHz Capacitance [fF] [fF] Vg[V] HfSiON SiON Frequency [GHz] HfSiON: Lg=58.6nm SiON: Lg=58.6nm 10GHz 10GHz 15GHz 15GHz 20GHz 20GHz Capacitance [fF] Capacitance [fF] Including overlap capacitance Vg[V] 10GHz 20GHz Capacitance [fF] Gate length L [nm] Gate length L+ΔL [nm] Vg[V] Intrinsic gate capacitance • Gate capacitance is constant at 10GHz~20GHz • Dielectric dispersion is not seen in this region
Conclusion • RF characteristics reflect DC characteristics • -High electron mobility cause high fT • fmax depend on finger length (Wf) -High fmax is gotten at Wf = 2um, which checks with simulation result • Gate capacitance degradation due to dielectric dispersion is not seen at 10GHz~20GHz • High-k MOSFET has potential ability even if at RF region